Slashing the cost of solid-state lightings
Apr 11, 2013
How can LED epiwafers costs fall to a level that can spur mass adoption of solid-state lighting? By turning to growth on 200 mm silicon substrates, loaded into a multi-wafer MOCVD reactor equipped with advanced thermal management and optimised wafer recesses, argues Aixtron’s Boerge Wessling.
The GaN-on-silicon LED is having a resurgence. It was a hot topic several years’ ago, and it is now its well and truly back in the limelight –LED chipmakers are now developing manufacturing processes for producing devices on this platform. If they succeed, they will slash the cost of this solid-state emitter. According to market analysts, switching from LED production on 100 mm sapphire, a common platform today, to 150 mm or 200 mm silicon should lead to substantial savings in the high double-digit level.
Slashing the cost of the LED promises to drive a hike in the sales of bulbs based on this technology. This is only possible, however, if a stable, reproducible epitaxy technology is available that enables LEDs grown on silicon to deliver similar levels of performance to those on the market today.
Recent announcements indicate that there are no longer major concerns regarding the brightness and efficacy of LEDs grown on silicon. Now the biggest barrier to high-volume, profitable production of this class of device is a sufficiently high yield. At Aixtron of Aachen, Germany, we are addressing this issue with the launch of our AIX G5+, an MOCVD system dedicated to the growth of LEDs on 200 mm silicon substrates (see Figure 1).
Figure 1. An Aixtron AIX G5+Planetary reactor, designed for the growth of five 200 mm GaN-on-silicon epiwafers
Requirements for high-yield epitaxy on large area substrates of silicon, or sapphire for that matter, include optimisation of the reactor temperature profile and precursor delivery. The AIX G5+ delivers on both fronts, thanks to an optimized RF heating coil and a novel gas inlet, which provides excellent gas flow stability and uniformity on the full batch area of 5 x 200 mm wafers.
The challenge of delivering high yield LED manufacturing is far tougher on silicon substrates than it is on those made from sapphire: In addition to uniform gas flow distribution and optimized temperature management, it requires minimization and management of silicon wafer bow. If the wafer deforms, this leads to undesirable non-uniformities in emission wavelength. To combat this, MOCVD processes must be developed that produce satisfactory chip yields. In addition to wavelength uniformity, the wafer must be flat when cooled to room temperature, to enable high-yield in various processing steps, such as lithography.
Origins of bow
Wafers start to bow when they are heated up to typical MOCVD process temperatures. This heating comes from the reactor’s wafer carrier, which heats the bottom of the substrate. In comparison, the wafer’s top surface is exposed to the process chamber, so it is at a lower temperature. The vertical thermal gradient that results across the wafer causes its expansion to be greater at its top than at its bottom. This leads to a spherical bow, which is more pronounced for thinner, larger wafers. Consequently, deposition on 200 mm substrates is particularly challenging.
The only way to address this heating-related bow is to control the temperature of the reactor wall facing the top
surface of the wafer. This feature is present on the AIX G5+, which accommodates a warm reactor ceiling that lowers the bow of a standard thickness 200 mm silicon wafer by up to about 30 percent compared to other reactors.
Bowing issues are exacerbated by differences in the thermal expansion coefficients of silicon and the nitride layers. During epilayer deposition, wafer bow evolves according to the strain characteristics and the thickness of the layers that are deposited. If the strain is not managed properly, the resulting bow leads to non-uniform wavelength characteristics, layer cracking, and even wafer breakage.
To prevent this from happening, strain management techniques are applied, such as the introduction of interlayers that have a strain that counterbalances that associated with the nitride layers. These strain reduction techniques can minimize bow during different growth steps, in order to prevent layer cracking, and ultimately they can lead to the formation of a flat wafer after growth and cool-down.
If these techniques are applied successfully, wafer bow is minimal. For example, it is possible to produce a 200 mm LED epiwafer on silicon with a bow of less than 10 µm (see Figure 2). The wafers, which have been grown in a reactor featuring in-situ
curvature measurement tools to monitor any deformations, are crack-free.
Figure 2. In-situ curvature measurement of a 200 mm GaN-on-silicon wafer. The nitride stack of films is 6 µm-thick, and features a multi-quantum well structure, a buffer and n-doped GaN. The wafer is crack-free, with remaining bow less than 10 µm
Although it is possible to minimise wafer bow with the techniques outlined above, it is impossible to eliminate it during the deposition process. This means that for the growth of the multi-quantum well structure, the key region within the device, it is critical to provide a uniform wafer temperature at a given wafer bow. It is possible to do this with the AIX G5+, because the wafer recesses can be customized to account for the thickness of the structure and the customer’s proprietary strain management techniques.
The design of the reactor determines whether a wafer will bow with rotational symmetry (to the form of a bowl) or warp (resembling a potato chip). If the wafer bows to the form of a bowl, the distance between the wafer’s edge and its carrier is the same along its entire circumference. This means that the temperature has a symmetrical profile and can be accounted for by recess designs. Adopting this approach is not possible if the wafer warps, because variations in temperature over its surface are much more complex.
It is only possible to realise rotational symmetry of the bow in either single wafer reactors, or in ‘Planetary Reactors’, such as the AIX G5+, where every wafer experiences an environment similar to that found in a single-wafer reactor. The benefits of symmetry extend beyond an increase in epitaxial binning yield, and include fewer handling issues and reduced yield loss in subsequent wafer processing steps.
An indication of the yields produced by five different wafer recess designs in an Aixtron AIX G5+ is presented in Figure 3. Variations in design lead to variations in wavelength distributions, and for the structure formed in this particular run, the best matched design delivers a yield of 95 percent in 5 nm bin (no edge exclusion). Extend the bin to 10 nm, and yield rockets to 99.97 percent.
Figure 3. Uniformity optimization in an AIX G5+ reactor (5 x 200 mm) using different susceptor pocket types (left); plot of optimized uniformity (right). Standard deviation is 1.3 nm.
Curvature of the wafer depends on several factors. It is proportional to thickness of the film and its stress, and it is inversely proportional to the square of wafer thickness (Stoney’s equation). So, in addition to using strain management layers and an optimised reactor to minimise bow, engineers can try to combine thin epilayers with a thick substrate.
Thin layers are advantageous for other reasons – they shorten growth times and the cost of the ingredients that are required to make the epiwafers. However, it is very tricky to trim the thickest part of any LED, the GaN buffer. Lattice mismatch between GaN and silicon is 17 percent, which is more than that between GaN and sapphire, and, in general, a thick buffer is needed to minimise epitaxial defects.
Process engineers select the thickness of the substrate based on the design of the deposited structure, its thickness, and their capability to manage wafer bow. Today, growth of LEDs on silicon is still in its infancy, and silicon substrates with a thickness of up to 1.5 mm are often used to develop this technology. This path is the simplest one to making GaN-on-silicon LEDs, but engineers will want to migrate to thinner wafers to enjoy cost benefits - a 1.5 mm-thick, 200 mm wafer is significantly more expensive than a 725 µm standard wafer. What’s more, the retrofit cost for existing 200 mm silicon processing lines can be minimized with thinner wafers.
Silicon substrates have another downside for LED growth – undesirable chemical reactions. Gallium can form an alloy with bare silicon, destroying its crystal structure at the substrate’s surface. To prevent this from happening, the sensitivity of silicon towards gallium must not only be taken into account when choosing the correct initial growth conditions, which is the use of AlN as a seed layer. In addition, approaches that prevent this gallium-silicon reaction from ever taking place must be considered when designing a multi-wafer, high throughput MOCVD reactor.
Reactions that must be prevented include the interaction of residual gallium atoms in the reactor, which were left over from the previous run, re-evaporating during the heat-up phase of a subsequent growth run and causing ‘meltback’ etching on the wafer. When this happens, it diminishes the quality of growth and impacts device yield. To combat this, methods have to be devised to prevent gallium from reacting with the bare silicon substrate.
In the AIX G5 HT series, which includes the AIX G5+, interaction of residual gallium with the silicon substrate is prevented with an approach that ‘resets’ the chamber. This equips it with well-defined, reproducible and clean starting conditions, and gives the chamber the best starting point for repeatable, stable run-to-run performance. A series of five consecutive runs of GaN-on-silicon structures using the same epitaxy recipe and the ‘reset’ methodology produces epiwafers with thicknesses within +/- 1 percent (see Figure 4). All wafers have comparable on-wafer uniformities, with standard deviations less than 1 percent (all data without edge exclusion).
Figure 4. Thickness variation of four consecutive growth runs in an Aixtron AIX G5+
Using this ‘reset’ approach on the AIX G5+ enables the production of high-quality, 200 mm GaN-on-silicon LED epiwafers. This reactor, which has been purpose-built for that particular task, provides: the industry’s largest throughput; a stable, repeatable epitaxy performance based on an automated chamber reset; and a unique kind of bow management, being able to deliver final bows of less than 10 µm for thick structures on 200 mm silicon. In short, it is the reactor for driving the lighting revolution.