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Gate dielectric process improves power GaN reliability

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Toshiba describes process for reducing impurities in the gate dielectric of GaN MOSFETs at IEDM

Toshiba has developed a gate dielectric process technology for improving the reliability of GaN power devices. Details of this technology were presented at the International Electron Devices Meeting (IEDM) in San Francisco on 6 December 2017.

Toshiba has traced the cause of variations in GaN-MOSFET threshold voltage to impurity traps within the gate dielectric, and has developed a process technology that can greatly reduce impurities in the gate dielectric.

Impurities such as hydrogen in the gate dielectric are substantially reduced by treatment to repair the damage that occurs during GaN semiconductor fabrication and then performing appropriate annealing of the gate dielectric.

Compared with conventional technology, this greatly reduces variation in threshold voltage and delivers world-leading gate reliability, according to Toshiba.

Toshiba is working on research and development with the aim of further increasing reliability in order to bring this technology into practical use.

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