Self-aligned growth spawns hybrid photonic devices
Miniature, high-performance optical links could be formed on silicon substrates through self-aligned growth in oxide tubes
BY SVENJA MAUTHE, NOELIA VICO TRIVIÑO, MARILYNE SOUSA, HEINZ SCHMID AND KIRSTEN MOSELUND FROM IBM RESEARCH EUROPE
SILICON MICROELECTRONICS has made staggering progress. The latest components have a footprint of just a few tens of square nanometres, consume very little power, and are packed in their billions on a chip.
Today’s technology, the culmination of decades of silicon CMOS processing development, has also spawned advances that benefit silicon photonics. Fabs can now produce low-loss silicon waveguides and passive structures to route optical signals through a chip. However, this technology is not perfect. Arguably its biggest weakness is the lack of optical gain, stemming from silicon’s indirect bandgap.
Free from this limitation are a portfolio of III-V compound semiconductors with direct bandgaps spanning the entire spectral range from the visible, using III-nitrides, to the near infrared (see Figure 1). The latter is of interest for optical communication, with bands around 1350 nm and 1550 nm – they are known as the O-band and C-band – providing the preferred choices for datacom and telecom, respectively. These bands have been adopted because they correspond to minimum transmission losses in optical fibres, and coincide with the availability of effective sources and erbium-doped fibre amplifiers (EDFAs). These spectral domains are also well suited for on-chip applications, thanks to silicon’s transparency at wavelengths beyond 1.1 μm. Due to this attribute, SOI waveguides can serve as a low-loss transmission medium.
Figure 1. Bandgap versus lattice constant for a variety of direct (full circle) and indirect (circle) semiconductors. The 8 percent lattice mismatch between silicon and In0.53Ga0.47As is highlighted. The blue shaded area corresponds to the telecommunication band.
An additional attribute of the ternary or quaternary III-Vs is that by adjusting their composition, the bandgap is varied, enabling the growth of quantum wells and dots. Consider, for example, the combination of InP and In0.53Ga0.47As, a pairing that share the same crystal lattice constant, enabling defect-free growth. The bandgap of In0.53Ga0.47As is just 0.74 eV, far less than the 1.35 eV for InP, so inserting an In0.53Ga0.47As layer between InP barriers creates a deep potential well that excels at confining excited electrons and holes and localising the recombination process. The opportunity to form quantum wells and quantum dots has been instrumental to the development of today’s efficient III-V lasers.
Uniting III-Vs and silicon
One of the holy grails of research within the semiconductor industry is the seamless integration of photonics and electronics, so engineers can draw on the best of both worlds. Today, the state-of-the-art approach to accomplishing this is to directly bond a wafer with a III-V active stack onto a pre-processed silicon wafer (see Table 1, which compares this approach to other techniques for integrating III-Vs on silicon). Wafer-bonding allows light to couple evanescently from underlying silicon waveguides to the active III-V regions above. Engineers have demonstrated highly advanced devices with this approach, integrating both detectors and lasers.
Bonding can also take place at the die level. In this case, individual III-V dies or pre-processed III-V devices can be united with a silicon platform. While these chips may seem small from the perspective of the III-V community, with dimensions of several hundred microns, they are far, far larger than electronic components. With transistors typically fitting within tens of nanometres, the size mismatch is about three orders of magnitude.
Table 1: Overview of existing technologies for integrating III-V materials on silicon. Reprinted with permission from  M. Seifried et al. IEEE JSTQE 24 8200709 (2018), doi: 10.1109/JSTQE.2018.2832654, licensed under CC BY 4.0;  S. Keyvaninia et al. Opt. Mater. Express 3 35 (2013), doi: 10.1364/OME.3.000035, ©2012 Optical Society of America;  I. Luxmoore et al. Sci Rep 3 1239 (2013), doi: 10.1038/srep01239, licensed under CC BY-NC-ND 3.0;  T. Katsuhiro et al. J. Phys. D: Appl. Phys. 47 394001 (2014), doi: 10.1088/0022- 3727/47/39/394001, ©2014 IOP Publishing Ltd, CC BY 3.0.
Gaining in popularity, monolithic growth offers another option for uniting III-Vs with silicon. This approach enhances integration densities, by depositing III-V material locally, only where it is needed. While this method has much appeal, its execution is challenging, partly because there is significant difference in atomic spacing of the respective crystal lattices (see Figure 1). For example, there is a lattice mismatch of about 8 percent between silicon and InP/In0.53Ga0.47As. This difference can result in numerous dislocations and anti-phase boundaries that hamper the performance of optical devices. Adding to the challenges of monolithic growth, different materials can have different thermal expansion coefficients, causing cracks and defects to appear when cooling the wafer down from its growth temperature, typically 550 °C to 700 °C, to room temperature.
A well-known approach to overcoming both these issues is to switch from growing a stack of layers to growing nanowires. The growth of III-V nanowires can begin with a metal catalyst (usually vapor-liquid solid type growth), or with an opening defined in a pre-patterned hard-mask on the surface of a silicon wafer, and approach known as selective-area epitaxy.
Our team at IBM Europe has trailblazed yet another technique for marrying III-Vs with silicon. Our approach, which we refer to as template-assisted selective epitaxy (TASE), involves the growth of III-Vs within oxide tubes formed on a silicon substrate (see Figure 2 for an outline of the process flow).
Figure 2. Template-assisted selective epitaxy (TASE) process flow and material investigation using scanning transmission electron microscopy (STEM). TASE is performed on an SOI wafer. The top silicon surface is patterned and covered with SiO2. Subsequently an opening is etched into the oxide shell on one side and the underlying silicon is partially etched. Using MOCVD, III-V material is grown from the remaining silicon into the empty SiO2 tube. Images reprinted with permission from S. Mauthe et al. Nat. Commun. 11 4565 (2020).
In our case, growth of the III-V begins with nucleation on a small silicon surface, exposed at one extremity within the hollow template. Just like the formation of nanowires, growth is monocrystalline, with typical defects from heteroepitaxy suppressed. We can produce larger or more exotic shapes by adapting the size of the template – however, for the work we discuss here, we only fabricate simple bars or nanowires. Unlike conventional nanowires, our structures are grown along the surface of silicon, enabling integration with photonic silicon structures.
It is interesting to note, however, that we did not develop TASE for photonics. Initially, we targeted electronic applications, using this technology to provide a complementary tunnel FET platform, which is described on pages 38 to 42 of the January/February 2017 edition of Compound Semiconductor.
There are two essential attributes of our TASE technology that enable us to form the devices described in the remainder of this article. Firstly, because our method relies on replacing existing silicon features by a III-V, it is self-aligned – the shape and position of the compound semiconductor material that we add is defined in the same lithographic step as the silicon features. Thanks to this, we can perfectly tune the coupling to waveguides, and we can insert scaled III-V features within a silicon photonic crystal lattice. The upshot is that we engineer truly hybrid structures, integrated seamlessly. Secondly, we can introduce doping profiles and composition gradients in-situ, during growth. One of the merits of the geometry that results from our process is that it makes coupling to silicon waveguides straightforward.
As optical signalling extends from server racks to on-board and finally on-chip schemes, demand for detectors will grow to thousands, if not millions. While an on-chip light source is highly desirable but not mandatory, densely integrated photodetectors are an essential ingredient in optical transceivers, required to process the incoming optical signal.
To successfully replace lossy electronic interconnects, it is critical that power-consumption is at the very least similar – and ideally lower – than that of comparable electronic interconnects. Efforts must focus on limiting RC constants, a requirement that can be accomplished with small-footprint devices with small capacitances. The key to satisfying these constraints is to transition away from today’s large, high-performance devices – and this is where III-Vs have an important role to play.