CS Mantech: Strengthening the credentials of the III-V transistor

Fast transistors are poised for far greater deployment, thanks to efforts by fabs and those working on internal production lines.

BY RICHARD STEVENSON, EDITOR, COMPOUND SEMICONDUCTOR

If you are a veteran of this industry, you will remember the days of GaAsMantech. At that conference chipmakers would champion breakthroughs in the design and production of III-V transistors serving in a variety of applications – primarily mobile communication.

It’s now been more than a decade since that conference series, always held in North America, changed its name CSMantech to reflect a greater diversity of devices. Over the intervening years the GaN HEMT has come on in leaps and bounds to dominate an agenda that also highlights advances in SiC power electronics and optoelectronic devices. However, the conference still provides a platform for reporting significant breakthroughs associated with the manufacture of III-V transistors.

At this year’s conference held in Monterey delegates detailed: the introduction of foundry services for making sub-terahertz transistors from 150 mm wafers; efforts at improving the manufacturing readiness of InP HEMTs that feature an InAs channel and can operate at hundreds of gigahertz; an overgrowth-and-plasma-treatment process promising to speed a novel HBT; and a hybrid etching process to boost the yield and breakdown voltage of a GaAsSb/InP HBT. Taken together, these advances should ultimately drive the deployment of better III-V transistors in 5G and 6G networks, in space, and in test and measurement equipment.

Faster foundries
For the manufacture of RF devices for mobile communication, providers of epiwafers and foundries have been playing a key role for many years. These players are currently developing and launching products that will allow design engineers to work with far higher frequency transistors.

One of the leading III-V foundries that is working on a portfolio of sub-terahertz transistors is WIN Semiconductors of Taiwan. According to Cheng-Kuo Lin, who spoke on behalf of the company at CS Mantech, new device designs are needed to reach this frequency domain. That’s because the company’s established technologies – the GaAs pHEMTs and InGaP HBTs that have been widely used in MMICs for power amplifiers, low-noise amplifiers and switches – are unable to provide sufficient power gain in amplifiers at sub-terahertz frequencies.

To provide customers with products operating at those very high frequencies, engineers at WIN have been developing three different technologies for production on their 150 mm line: InP HBTs, and metamorphic and pseudomorphic HEMTs with a gate length of just 100 nm.

Lin told Compound Semiconductor that the strengths of the mHEMT are its ultra-low noise and its high gain in the D-band, which spans 110 GHz to 170 GHz. In comparison, the pseudomorphic HEMT majors on the maturity of its epitaxial process and the device’s higher operating voltage. “The limitation could be the operating frequency,” remarked Lin, who argued that for frequencies above 170 GHz, the InP HBT is a stronger candidate that is capable of integrating more RF function blocks.

The 150 mm epiwafers for WIN’s pHEMTs are grown by MOCVD on GaAs substrates and feature an indium-rich InGaAs channel that provides high mobility, ensuring excellent carrier transport. GaAs substrates also provide the foundation for the mHEMTs, grown by MBE. These epiwafers, which also have an InGaAs channel, use a metamorphic buffer to trap dislocations and adjust the lattice constant from that associated with GaAs to that for InP.

Compared with another device, the InP HEMT, the metamorphic HEMT delivers comparable performance for significantly less expense. As well as a higher price for the substrate, the epi for the InP HEMT is more expensive, due to a longer growth time. Another factor in favour of the mHEMT is that its epiwafers are more widely available than those for InP HEMTs, due to the difference in the substrate.

The 100 nm gate lengths of the mHEMTs and pHEMTs, which hold the key to reaching higher frequencies, are formed by electron-beam lithography. Production of the pHEMT also involves: the addition of source and drain ohmic contacts, device isolation by ion implantation, SiN passivation, and the formation of a 2 µm air bridge. Fabrication of the mHEMT employs similar steps, but isolation is carried out by wet etching.

To assess device uniformity, WIN’s engineers produce maps of wafer uniformity. These plots reveal a threshold voltage variation, in terms of one- σ, of just 17 mW and 16 mV for pHEMTs and mHEMTs that populate these 150 mm wafers. The low values, claimed to be an industry milestone, confirm that the gate is able to control the channel without any concern over leakage. The implication for customers is that they can expect to get a high product yield from these wafers.

Measurements of the maximum available gain put the InP HBT out in front, and the mHEMT ahead of the pHEMT (see Figure 1). This plot suggests that the maximum oscillation frequency (f_max) is 353 GHz for the HBT, 321 GHz for the mHEMT, and 247 GHz for the pHEMT. The pHEMT produces the highest power density of 724 mW/mm, compared with 248 mW/mm for the mHEMT and 2.59 mW/µm² for the HBT.

All three classes of transistor have undergone high-temperature operating lifetime tests. For the mHEMT, testing involved 500 hours of operation at an ambient temperature of 165 °C and a drain voltage of 2 V. Under these conditions the threshold voltage, the transconductance, the maximum drain current and the gate leakage shifted by less than 20 percent, leading engineers to conclude that the mHEMT passed this test. Also passing its test is the pHEMT, while the HBT is still under investigation.

Thanks to the positive results with the pHEMT, this device is now available to customers, which can use WIN’s process design kit (PDK) to create their MMICs. For the mHEMT the process is finalised and the PDK ready, but it will be the end of this year before an official release. However, customers can already participate in “early engagement”, according to Lin.

Engineers will continue to improve the HBT before it’s released. “We’re going to get higher performance by optimising the emitter size from 0.8 micron to 0.5 micron,” remarked Lin, who revealed that our team’s plans extend to adding a copper-pillar to the HBT wafer to minimise deleterious effects associated with wire bonding.

Refining the process
At Northrup Grumman much effort is being devoted to improving production processes for transistors that feature an InAs composite channel and operate at frequencies approaching 1 THz. Two decades of development, funded by agencies associated with the military, has helped drive this technology’s development and take it to a manufacturing readiness level of 3 to 4 – this means that devices can be produced in a lab. Now work is underway, outlined at CSMantech by Northrop Grumman’s Feifei Lian, to improve the maturity of this device’s production process. The aim is to close the gap with the company’s InP HEMT technology, which is capable of producing devices in volume on an internal 100 mm line.

Lying at the heart of this emerging generation of devices from Northrup Grumman is a high-electron-mobility InAs channel. Responsible for the transistor’s high frequency and low power prowess, this channel is clad by a pair of lattice-matched InGaAs layers. Additional features of this transistor are its low-resistance ohmic contacts, realised by the inclusion of a Schottky barrier layer and a heavily doped cap in the epitaxial structure, and T-gates with dimensions from 25 nm to 70 nm, defined by electron-beam lithography.

To advance the manufacturing readiness of these devices, Lian and co-workers have had to transfer their MBE growth process from a single-wafer tool, used to produce a 75 mm epiwafer, to a multi-wafer MBE reactor that accommodates multiple 100 mm wafers. Encouragingly, the average value for the electron mobility in the channel is higher for wafers produced with the multi-wafer tool. Initially, growth on this higher-throughout reactor led to a larger variation in the ohmic contact resistance for the HEMTs, but this issue has been resolved by modifying the doped cap design.

Figure 1. WIN Semiconductors has developed three new foundry processes for producing III-V transistors for millimetre-wave applications on a 150 mm line. The InP HBT process provides the highest gain, followed by the 100 nm mHEMT and pHEMT processes.

Lian and colleagues have also taken a close look at the gate formation process, which must be carefully tuned to consistently realise uniform electrical characteristics and a high gate yield. The gate recess is key, as it influences many device characteristics, including transconductance, the pinch-off voltage and breakdown. If there is poor control over the gate recess depth, this can result in enhancement-mode devices with extremely thin Schottky barriers, a very high gate leakage, poor noise and compromised reliability, due to metal diffusion.

To try and improve the gate formation process, engineers at Northrop Grumman have investigated two potential refinements to their gate formation process. One involves using an optimised wet etch processes and semiconductor surface treatments to ensure a uniform etch initiation and progression; and the other introduces an etch stop process, with the wet etch stopping on a layer embedded in the barrier. The latter leads to excellent uniformity, but often at the expense of a reduction in device performance (see Figure 2). To increase the process margin, etch-stop processes can employ a significant over-etch, but this widens the recess region, increases access resistance and ultimately diminishes device gain.

Figure 2. To improve the manufacturing readiness of its HEMTs that feature an InAs composite channel, engineers at Northrup Grumman have been developing a new process for the gate recess etch. The original process produces a poor gate recess etch uniformity (a). This is improved with an optimised gate recess etch (b), while an even smaller variation is yielded with a selective gate recess etch.

Lifetime testing on HEMTs produced with the selective gate recess etch show a projected mean-time-to-failure of 1.9 x 10⁷ hours at a junction temperature of 125 °C. According to the team, this indicates that these devices have sufficient reliability to serve in space missions that are categorized as class A, which means that failure would have extreme consequences to either public safety or to high-priority national science objectives.

Advancing instrumentation
For those that have been increasing the high-frequency capability of SiGe BiCMOS technology, much progress has come from the introduction of an epitaxial regrowth step for the SiGe base. This refinement has increased f_max, along with the current gain cut-off frequency (f_T) and the ring oscillator delay. Today’s state-of-the-art BiCMOS processes employ either a selective or a non-selective re-growth of a highly doped base – this trims base resistance and improves high-speed performance, allowing designers to use faster transistors or enjoy a wider design margin.

At Keysight Laboratories, engineers are investigating whether there is a similar opportunity for their GaAsInP/InP double HBTs, which are widely used in the company’s high-speed test and measurement instruments. Speaking on behalf of this vertically integrated instrumentation maker at CSMantech, Barry Wu described a low-temperature GaAsSb extrinisic base regrowth process involving an in-situ hydrogen plasma treatment and MBE non-selective regrowth of the base. This promises to build on Keysight’s double HBT technology platform that already has tremendous high-speed capability. In its latest guise, this is capable of producing a 0.5 µm device with an f_T of 280 GHz and an f_max of 580 GHz.

The company’s latest investigations have involved a Veeco Gen200 multi-wafer MBE system and a Veeco UNI-Bulb hydrogen remote-plasma source with an RF generator. These tools are connected, allowing wafer transfer under ultra-high vacuum.

Figure 3. Engineers at Keysight Technologies have started to investigate the benefits of hydrogen plasma treatment to reduce the base resistance in their double HBTs. Slashing the oxygen content trims the base resistance by 30 percent, an encouraging sign for speeding the transistor.

Prior to plasma treatment and regrowth, epiwafers with a 250 nm-thick GaAs_0.51Sb_0.49 layer underwent typical III-V semiconductor fabrication processes, such as ashing and wet de-oxidation. Following plasma treatment, the wafers were loaded into the MBE system, used for the re-growth of a 50 nm-thick layer of GaAsSb doped to about 5 x 10²⁰ cm^-3.

Engineers at Keysight considered the impact of variation in treatment time, and also the influence of fab processing. According to secondary-ion mass spectrometry, plasma treatment for 105 minutes decreased the oxygen profile by
a factor of around 50 (see Figure 3). This technique also revealed that the oxygen concentration is significantly lower at the regrowth interface than the epilayer-substrate interface; and that the carbon doing level in the regrown GaAsSb is more than 1 x 10²¹ cm^-3, which is sufficient for an extrinsic base.

Measurements on Keysight’s wafers show that regrowth of an extrinsic base layer led to a 30 percent fall in the base resistance. Encouragingly, this reduction did not impact uniformity, with a tight intra-wafer uniformity retained (see Figure 4).

According to Wu, a lower base resistance has several benefits, including holding the key to improving the IC ring oscillator frequency, which enables a faster IC speed. It also helps to trim the noise figure and improve bias stability.