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Technical Insight

FinFET process pushes gate lengths below 50 nm

With it becoming increasingly difficult and expensive to reduce the limits of lithography any further, researchers are now looking at new ways to shrink feature sizes.
The combination of surface topography and dry etching inevitably leads to the formation of sidewall spacers. When materials are deposited by CVD or sputtering processes they typically cover topography in a conformal manner. This means that the vertical thickness of the material deposited at the edge of a step approaches the thickness of the material deposited in flat regions, plus the height of the step. As a consequence, when flat field areas are cleared during dry etching, unetched material will remain at the edge of the steps - the spacer. This sidewall spacer, the width of which is the thickness of the deposited layer in the field regions, can only be removed through additional etching. However, rather than viewing this as an etching problem, it has recently been realized that this can be exploited as a lithography technique. Instead of etching away the sidewall spacer, the material that formed the step is selectively etched leaving behind a free-standing spacer, the width of which is the thickness of the original deposited material.

This approach has been pioneered by researchers at the University of California at Berkeley in the fabrication of CMOS FinFETs, so called because the free-standing sidewall spacers resemble fins. The researchers fabricated sub-50 nm features - dimensions that can typically only be achieved by advanced E-beam lithography techniques (Choi et al.a,b).

FinFETs should be of a great deal of interest to the III-V community for two reasons. They have the potential to push today s state-of-the-art CMOS production gate lengths from the current 125 nm to the sub-50 nm regime, providing large performance gains. But even more importantly the sub-50 nm capability of the FinFET approach is just as applicable to III-V materials, for example in the implementation of sub-50 nm gates for MESFETs and PHEMTs.

FinFET fabrication

The Berkeley researchers implemented a FinFET process for nanoscale CMOS applications, fabricating fins as narrow as 6.5 nm and gate lengths of 30 nm for both NMOS and PMOS devices. The process flow is shown in the figure. SOI substrates are typically utilized, in which the starting 100 nm silicon film above the buried oxide is thermally oxidized, giving a 50 nm surface oxide that protects the remaining 50 nm silicon layer during fin formation. As shown in the figure (a), a 200 nm SiGe layer is deposited by low-pressure CVD and patterned into sacrificial structures that will be used to form the sidewall spacers.

A vertical profile on the SiGe sacrificial structures is crucial in order to fabricate fins of minimal and controlled widths (sloped sidewalls produce larger sidewall spacer widths). Phospho-silicate glass (PSG) of 30 nm thickness is then deposited, and a subsequent anisotropic PSG spacer etch is performed to remove the PSG everywhere except at the sidewalls of the SiGe sacrificial structures. The SiGe structures are then selectively etched away leaving behind the free-standing PSG sidewall spacers, as shown in the figure (b).

Next, the source/drain regions are defined by conventional lithography, and the active region of the FinFET devices is defined by the combination of the photolithographically defined source/drain regions and the hard-mask PSG spacer fins. The active region is then transferred to the underlying hard oxide mask and SOI film by dry etching. Once the spacer PSG fin and the oxide layer beneath it are etched away, a free-standing silicon fin-gate connected between the active source and drain regions remains. The width of the gate is that of the original PSG fin, though slight undercutting, which reduces the gate width by a small amount, may occur during etching.

The remainder of the process is fairly conventional, including the growth of a 2.5 nm gate oxide. The deposition of in situ doped poly SiGe is used for the gate material, which in turn is defined through conventional lithography (E-beam or optical). A standard ion implantation is used for the source/drain regions. The figure (c) illustrates the final dual-gate FinFET structure.

An obvious point of concern for such a structure is that the sidewalls of the active silicon channel have been defined by dry etching. This has the potential for sidewall damage in the form of surface states that could highly degrade carrier transport through the channel. Additional wet etching can be performed in an attempt to remove this damage, but this remains a critical area of further development for this structure.

Performance figures

The fabricated PMOS devices exhibited a drive current of 350 µA/µm and a turn-on voltage (Vt) of -0.76 V, while the NMOS device had a drive current of 400 µA/µm and a turn-on voltage Vt of -0.13 V. Both the devices operated at a bias (Vg-Vt) of 1 V and a Vd of 1 V. Unlike these FinFET devices, in a conventional CMOS process the NMOS drive current would be at least twice that of the PMOS. The observed increase in drive current for the NMOS FinFET device is a symptom of inadequate dry-etch damage passivation of the gate sidewall.

Future improvements

These devices are obviously not yet ready for production. However, the approach clearly shows that sub-50 nm gate length devices can be made which do not depend on highly sophisticated, expensive and often low throughput tools, but simply on the thickness of a deposited layer. Two things that could improve device performance are better passivation of the channel sidewall and the deposition of metal overlayers on the gate. These layers would reduce gate resistance (critical for RF applications), which will be extremely large in such a narrow gate width device. With these improvements, the FinFET has the potential of taking CMOS into both high-speed and high-frequency regimes that will compete with the highest performance III-V devices. However, as noted earlier, the same sidewall-lithography processes can also be applied to III-V materials, further improving their device performance too.

Further reading Y-K Choi et al. 2002a IEEE Elec. Dev. Lett. 23(1) 25.
Y-K Choi et al. 2002b IEEE Trans. Elec. Dev. 49(3) 436.

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