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IEDM Showcases Power HFETs

III-V device highlights at the 2005 International Electron Devices Meeting held in Washington, DC, included high-power GaN HEMTs with both single and dual field plates, and metal-insulator-semiconductor structures producing very low leakage currents. Richard Stevenson rounds up.

The IEEE s International Electron Devices Meeting (IEDM) is always dominated by silicon devices, and this year s conference proved no exception. However, the organizing committee also chose to squeeze in a session on one of the hottest research topics in compound semiconductors - GaN high-power transistors for RF and microwave applications.

The session began with Nitronex detailing the development of 368 W GaN-on-silicon HFETs that feature a field plate (FP) connected to the transistor s source electrode and extending to the center of the gate-drain region. The addition of this source field plate (SFP) is thought to be a critical development, enabling high output power and drain efficiency at high drain voltages.

Nitronex CTO Kevin Linthicum and a team of engineers compared the performance of GaN HFETs with and without an FP. Both types of device were fabricated on high-resistance silicon (111) substrates with gate lengths of 0.7 μm, and gate-to-source and gate-to-drain spacings of 1 and 3 μm, respectively. The single-chip transistors, which have a 36 mm gate periphery, were then packaged using a gold-silicon eutectic die attach in industry-standard RF packages with a two-stage input match and no output match.

Pulsed RF power measurements at 2.14 GHz using a 1% duty cycle and a 300 μs pulse width showed that the SFP device delivered 368 W with a maximum drain efficiency of 70% and 17.5 dB of small signal gain at a 60 V drain bias. The device without the SFP produced just 225 W at a lower drain voltage, with a drain efficiency of just 33%.Adding field plates

NEC engineers have taken the idea of improving transistor performance by adding FPs one stage further, by fabricating an AlGaN/GaN dual FP FET on a semi-insulating SiC substrate (see figure 1). The first FP forms part of the gate and improves the transistor s breakdown characteristics while suppressing current collapse. The second FP, formed on the SiN film at the gate edge, is connected to the source. This shields the electric field between the first FP and the drain, eliminating the high gate-drain capacitance seen in single FP structures.

Comparing the performance of single and dual FP FETs, the NEC team found that at a 40 V drain bias the dual FP transistor delivered an extra 3 dB of stable gain compared with the single FP device. On-wafer load-pull measurements revealed that the dual FP FET had wider stable load impedance, allowing easy tuning at maximum power.

The dual FP FET also showed greater linearity, with a 5 dB improvement in adjacent channel leakage power ratio over the single-plate versions. The researchers claim that the dual-plate device produces a state-of-the-art combination of 160 W output and 17.5 dB linear gain at 2.15 GHz, with wideband code division multiple access (W-CDMA) modulation and a 45 V drain bias.Uncovering the traps

Meanwhile, the Alcatel-Thales III-V laboratory outlined its evidence for trapping phenomena and trap creation in GaN-based HEMTs on SiC, thanks to a collaboration that included the universities of Padova and Bordeaux and France s Institute of Electronics, Microelectronics and Nanotechnology. The work, which should help the community improve its understanding of failure mechanisms in GaN transistors, is claimed to be one of the longest tests published for this type of device.

The 3000 hour transistor test involved a 25 V drain voltage, with the gate voltage adjusted to maintain 6 W/mm of dissipated power to define the on-state, and drain and gate voltages of 46 V and -6 V, respectively, for the off-state. Channel temperatures were 260 °C and 130 °C for the on- and off-states.

The on-state produced the most detrimental effect on drain current. Since the transistor s metal contacts were stable, the researchers concluded that degradation was probably caused by hot electrons in the active area during on-state stress.

Later in the session, a Fujitsu Laboratories team detailed GaN-based metal-insulator-semiconductor (MIS) HEMTs delivering 110 W and 13 dB of linear gain at 2.14 GHz. Toshihide Kikkawa and colleagues say that GaN HEMTs tend to suffer from high gate leakage currents under large RF input signals that degrade device performance and reliability. However, Fujitsu s AlGaN/GaN MIS-HEMTs showed only small leakage currents under high-voltage and high-power operation.

Analysis of the MOCVD-grown MIS-HEMTs revealed that the reverse and forward gate leakage currents were two and six orders of magnitude lower, respectively, than a Schottky gate HEMT operating under identical conditions. The MIS-HEMT also delivered a breakdown voltage in excess of 400 V, which the Fujitsu researchers claim is the highest ever reported for this type of device.

IEDM 2005
Washington, DC,
December 5-7, 2005
Organized by: IEEE
Delegates: 1730
Technical sessions/papers: 41/240
IEDM 2006 will be held in San Francisco, CA, on December 11-13

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