Simulations Provide Additional Insights Into GaN HFET Reliability
GaN HFETs are attracting considerable attention as high-power and high-frequency devices for radar, avionics and wireless base-station transmitters, thanks to the unique material properties of III-N material. However, the commercialization of these devices has been hampered by reliability issues that have been attributed to carrier trapping in either the bulk or surface of the device. These problems are being addressed by experimental studies that can produce epitaxy- and processing-related improvements, and simulations that can optimize device design.
Simulations provide key insights into device operation and the degradation mechanisms that affect reliability. They can contain structural details such as layer thicknesses, doping profiles and trap concentrations. The software-based approach can also aid the tailoring of a structure to specific market applications requiring particular performance characteristics, and can be an effective tool for selecting and optimizing the design.
In the silicon industry, process and device simulation - referred to as technology computer-aided design - is widely used to develop and optimize various technologies ranging from highly scaled CMOS to power management, non-volatile memory and image sensors. Over the past decade this approach has also been increasingly used for III-V technologies, and recent advances to III-N devices has promoted the use of simulation for improving GaN HFETs.Investigating current collapse
At Synopsys we have built the simulator software Sentaurus Device (see "Simulation software") to explore a physical mechanism that is referred to as either current collapse or dispersion, and is defined as the drain current (ID) degradation under operational or stress conditions. This mechanism limits GaN HFET reliability and is consequently inhibiting device commercialization. However, its origin is still under debate despite the various models that have been proposed, such as electron trapping in the GaN buffer and AlGaN barrier layers, and at the surface (Binari et al. 2002, Vetury et al. 2001).
Our simulations can help to understand the nature of current collapse, provide a detailed insight into device operation, and point towards mitigation strategies to avoid current collapse. However, they cannot predict the formation of non-ideal device properties such as traps.
The software has simulated a GaN HFET (see figure 1) with a room-temperature Hall mobility of 1100-1200 cm2/V-s and sheet carrier concentration of 8-9 × 1012 cm-2 (Braga et al. 2004). The calculations used values for the band structure, carrier mobility and saturation velocity of GaN, InN and AlN that are shown in table 1. Interpolation of the corresponding binary parameters provided values for AlGaN and InGaN.Trapping behavior
To investigate trapping behavior and gain insight into the current-collapse mechanisms, we inserted a background of acceptor/electron bulk traps with a density of NT = 5 × 1017 cm-3 into our model of this particular device. Since the motivation behind this study is to obtain a qualitative insight, the traps were defined with a single energy level 1 eV above mid-band. However, our simulation software can accommodate multiple trap levels that are commonly ascribed to GaN epitaxial material (see Binari et al. 2002) in either the bulk or at the surface.
Using these conditions we could match our simulations of direct-current (DC) I-V characteristics with measured data if we used an interface charge of 1.15 × 1013 cm-2 and an electron saturation velocity that is 40% of the theoretical bulk value. The value used for the interface charge, which equates to a partially relaxed AlGaN layer, is lower than that associated with theoretically-ideal strain conditions, which would have a value of 1.5-1.7 × 1013 cm-2. However, this value is consistent with observations from several experimental groups who have seen a reduction of the piezoelectric component. A reduction in saturation velocity has already been proposed, due to modified scattering of the two-dimensional electron gas (2DEG) at the heterointerface.
We also compared the experimentally-measured DC ID-VD output characteristics with simulations that both ignore and include hot-electron effects (see figure 2). Our drift-diffusion (DD) model assumes that the carriers are in thermal equilibrium with the lattice, while the hydrodynamic hot-electron compatible (HD) model accounts for carrier heating and non-local electric field effects. The measured and simulated curves created with the hydrodynamic model have a decline in their ID value after the peak - known as a negative differential conductance - that is absent in the curve produced with the DD model. We believe that this feature is not attributable to self-heating (Deng et al. 1999), but is in fact evidence for hot-electron capture at bulk traps under sufficiently high drain bias.
The HD model also shows that at large drain biases electrons in the channel are significantly heated and can exit the AlGaN barrier and then spread toward the GaN bulk - an effect that is not predicted with the DD model (see figure 3). At these high drain biases electrons occupy more traps. This increases the energy of the conduction band under the gate edge located toward the drain, and creates a potential barrier to electron flow.
The loss of electrons from the drain channel, which leads to current collapse, can be prevented by improving the electron confinement in this region. In fact this improvement has already been observed in a AlGaN/ InGaN/GaN double heterojunction FET structure that features a potential barrier between the InGaN channel and the underlying GaN layer (Simin et al. 2001).
We simulated the effect of the potential barrier on current collapse by carrying out transient simulations at differing indium concentrations that are akin to gate-lag measurements. These HD simulations involve setting the drain voltage to 0.1 V and giving the gate a 1 µs gate pulse from 0 to -5 V, which is then restored back to 0 V. These simulations confirm the improvement in current collapse resulting from the use of InGaN layers to provide superior channel confinement of the 2DEG.Field-plate enhancements
One of the most compelling attributes of GaN HFETs is their high-voltage operation, which produces a higher output impedance and wideband impedance matching. Recent work suggests that field-plate structures are effective at reducing current collapse at high voltages ("Agilent delivers E-PHEMT PAs with low-voltage operation" Compound Semiconductor January/February 2006, p25). This is because field plates reduce the electric field at the drain-edge of the gate, which leads to a lower electron temperature.
We investigated the electron temperature in GaN HFETs with no field plate, a source field plate and a gate field plate. When the device is built without a field plate, hot electrons diffuse into the bulk and are trapped, but when a gate field plate is used, the electron temperature is reduced (see figure 4).
The impact of field plates on current collapse can be assessed with transient simulations. Using conditions identical to those for the transient simulation already described, but with the exception of an increase in the drain voltage to 6 V, revealed that the gate field-plate structure yields an almost complete recovery of the drain current, indicating very small gate lag (see figure 5). This analysis is consistent with reduced hot-electron diffusion and trapping, and shows that the addition of field plates will improve device reliability.
Our hot-electron-based model of current collapse suggests a different mechanism from the "virtual gate" model, which argues that high electric fields at the drain-edge of the gate cause electrons to be injected from the gate into surface traps (Vetury et al. 2001). However, since surface trapping of electrons is well known in compound semiconductors, it is plausible that both models play a role in current collapse.
We believe our simulations, which show that field plates and double heterostructures can suppress the hot-electron effects in the bulk region of a transistor, can accurately model device behavior, and are an invaluable tool for optimizing this promising technology toward its eventual commercialization.Acknowledgments
We would like to thank Michael Shur of the Rensselaer Polytechnic Institute, Remis Gaska of Sensor Electronic Technology, and Grigory Simin and Asif Khan of the University of South Carolina for guidance and experimental support.References
S C Binari et al. 2002 Proc. IEEE 90 1048.
N Braga et al. 2004 J. Appl. Phys. 95 6409.
J Deng et al. 1999 MRS Fall Meeting Proceedings.
G Simin et al. 2001 Jpn. J. Appl. Phys. 40(2) L1142.
R Vetury et al. 2001 IEEE Trans. Elec. Dev. 48 560.