Japan Eyes Communication Networks With Record-breaking Transistors
The Japanese and US governments have different reasons behind their funding of national GaN transistor development programs. While the US sees the technology as a key to its next generation of military hardware, Japan believes that GaN transistors can form the heart of tomorrow s civilian communication systems.
Japan hopes that the GaN HEMTs can replace the silicon and GaAs chips that are employed to amplify the signals of today s base stations used for wireless networks. The relatively low output power of the incumbent transistors means that several of them have to be used together in large and inefficient power-combining circuits. These drawbacks could be overcome, however, by using a single GaN transistor that is more powerful. The stronger signals could also improve automotive radar s detection range and boost the reliability of the associated modules, thanks to GaN s reliability at the high temperatures found within a car.
To create the devices for these applications, Japan launched a five year program in September 2002 that has funding of Â¥3 billion ($25 million) (see figure 1). The money is fed through Japan s New Energy and Industrial Technology Development Organization (NEDO) and involves four main organizations: Risumeikan University, the government s National Institute of Advanced Industrial Science and Technology (AIST), Toyoda Gosei and NEC. Each of these organizations is responsible for different aspects of the development, like material and wafer development or device design (see figure 2). According to Yasushi Nanishi, the program s leader and a professor at Risumeikan University, this horizontal approach is needed because of the difficulties of GaN development.Ambitious targets
Nanishi says that the program is going well and has delivered steady improvements in device performance. He is clearly a master of understatement, for the program has produced the world s highest output transistor chips at 2, 5 and 26 GHz. These advancements makes the project on-track to hit its final targets that include outputs of 200 W at 5 GHz and 20 W at 26 GHz, a material mobility of 2000 cm2/Vs, a sheet carrier concentration of 3 × 1013 cm2, and thickness and uniformity specifications of ± 5% on 4 inch substrates.
The high output power of NEDO s transistors results from a design that features a recessed gate FET and a field modulating plate (FP). The planar FP significantly reduces current collapse, a degradation of the drain current under operational or stress conditions, while further gains are made with a recessed design. These changes also improve the breakdown voltage from 50 V to 160 V and then 200 V.
Implementing the design has driven a rapid performance improvement in the output power of the projects FETs that are grown on semi-insulating SiC substrates. For frequencies of around 1.5 GHz, the L-band used in mobile phone networks, output power has rocketed in recent years (see figure 3).
There has been similar success at 2.14 GHz, a frequency used for CDMA cellular base stations. Reports last year described a single-ended 280 W amplifier and a paralleled gate design delivering 371 W, and this year the bar has been raised to 416 W. "We have matched the needs for commercial deployment," explains Nanishi, revealing that progress came from "small advancements" such as optimizing the circuit and the production process.
vAmplifiers that operate at 2.14 GHz have also been fabricated with a second FP. "This shields the capacitance between the gate and drain, minimizes feedback capacitance and increases the gain," explained Nanishi. This has produced an amplifier that delivers 160 W at 17.5 dB of linear gain under a 2.15 GHz W-CDMA modulation scheme.Targeting tomorrow s networks
The team have also made efforts to improve the output power of 5 GHz amplifiers for 4G networks and satellite communication systems. In 2005 the team reported a single-chip amplifier with a 61 W output, and this year it has announced a 100 W version that can deliver 12.9 dB of linear gain and 31% power added efficiency at a drain bias of 56 V. In pulsed mode output is boosted to 155 W. Toshiba, which is working outside the NEDO program, has produced even higher powers of 174 W at 6 GHz but this features four separate chips. Both results are short of NEDO s 200 W goal, but Nanishi says that he is very confident that his team will hit the target before the project is wound up early next year.
At 26 GHz NEDO s best published results are for amplifiers based on 0.25 μm T-shaped gate devices that deliver 5.8 W and a linear gain of 9.2 dB. However, Nanishi says that more impressive results have been produced in the lab and he expects that reports of amplifiers with outputs exceeding the 20 W goal will emerge.
At the core of all of these performance improvements are a range of characterization methods like photoluminescence, Raman spectroscopy, Kelvin probe microscopy and device performance simulations.
Photoluminescence studies with an ultraviolet lamp have revealed that more intense yellow emission from the buffer layer is related to higher leakage currents (see figure 4). This emission has been used to optimize the growth process for the buffer.After the team established the buffer s growth conditions they investigated the influence of this layer s thickness on leakage current. The results are contrary to what one would expect. "Usually, to obtain higher performance devices we should make the buffer layer thicker to obtain a higher-quality two-dimensional electron gas structure," says Nanishi. "But what we have discovered is that reducing the buffer layer thickness reduces the leakage current."
According to him even very thin buffer layers, which lead to increases in threading dislocation density, can produce good results because of the very high carrier concentration in the two-dimensional electron gas. Recent discussions revealed that other groups outside the NEDO program had also observed a similar relationship between the buffer layer thickness and leakage current.
Temperature profiles of the HEMTs can identify the chip s highest temperatures and lead to device improvements. "The dimensions of our structures are just a few microns, which means that Raman spectroscopy is the only way to measure temperature," explains Naishi. An unexpected shift in the position of hottest area with drain-source voltage was also observed using this method (see figure 5).
The team has also determined the electric field distribution within its devices by scanning cross-sections of HFETs with a Kelvin probe force microscope. This approach, which is similar to atomic force microscopy, has identified the high electric field gradient between the gate and drain contacts, which probably limits the transistor s breakdown voltage (see figure 6).
In addition to all these measurement techniques, computer models are now being used to simulate device behavior and optimize gate design. This approach could ultimately drive improvements in reliability, which is not actually one of the goals of the project.The absence of any reliability target is not an oversight, explains Nanishi, although the project is seeking technologies that are reliable and cost-effective. "The final developments for cost and reliability should be carried out in private companies, and will be the major works after this project finishes." Shipments of reliable devices developed during the NEDO project are expected within two years, so it should not be long before we can all reap the benefits of this program.