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Glasgow gets $2.5m for CMOS future

The Semiconductor Research Corporation sets Glasgow University the challenge of finding the best material for p-channel CMOS MOSFETs, for feature sizes down to 8 nm.

Glasgow University is about to embark on a $2.5 million project to identify the best compound semiconductor material for use in future generations of CMOS technology.

The three-year program is funded by the Semiconductor Research Corporation (SRC), which in turn gets its funds and priorities from industry leaders such as AMD, IBM and Intel.

“Being able to utilize MOSFETs in compound semiconductors has been the elusive Holy Grail of scaling for 30 years,” said Jim Hutchby of the SRC. “With what we expect to accomplish with the University of Glasgow, we may be only 2-3 years away from achieving that breakthrough.”

A CMOS gate features both a p-channel and an n-channel MOSFET. In SRC s strategy to continue improving CMOS performance Glasgow will identify material for the p-channel, and the SRC-bankrolled Non-Classical Research Center will develop a III-V n-channel.

Glasgow s program is due to start on January 1 2008, and the SRC says it expects to see results than can bring circuit feature sizes down to 8 nm. In comparison, Intel s newest Penryn processors feature 45 nm technology. The Glasgow project will add four to six years of continued circuit miniaturization to what current technologies can provide, according to the SRC.

Iain Thayne, the University of Glasgow project leader, says that the money will go predominantly on additional researchers, materials and testing apparatus. His group already has several of the key pieces of capital equipment in place at Glasgow s Nanoelectronics Research Centre.

Making III-V logic real
The p-channel effort at Glasgow will initially develop strained InGaAs structures. “We re going to move up in indium concentration, I suspect,” Thayne commented.

Thayne also says that the research will be strongly influenced by the work of Scott Thompson at the University of Florida. He says Thompson introduced the strain concepts for Intel's 90nm node.

“Scott did some really nice papers recently on orientation dependence in III-Vs - all theoretical calculations,” Thayne said. “We d like to emulate those experimentally.”

The reputation enjoyed by Thayne and Glasgow has grown through collaborating with Freescale Semiconductor and the establishment of the Nanoelectronics Research Centre. However, he sees this deal as a particular validation of his department's focus on compound semiconductors.

“For us the key thing is that we ve got some global recognition of the work that we re doing,” Thayne said. “About six years ago - actually at this time of year, at a Christmas retreat - we were thinking Where are we going with all the III-V technology that we've got? ”

“At that time our high-k dielectrics were starting to emerge and you start to say, Well if you go with the high-k, then all of the advantages of silicon dioxide go out the window . If that's the case, then why should you stick with the mediocre transport properties of a material like silicon?”

Connecting the Compound Semiconductor Industry

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Delegates attending these sessions will gain insight into device technology, find out about the current status and the roadmap for the compound semiconductor industry, and discover the latest advances in tools and processes that will drive up fab yields and throughputs.

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