IQE provides epitaxy for US graphene project
Epitaxy foundry IQE has joined a new research project that is aiming to develop high-speed transistors based on carbon atom monolayers.
The UK company s molecular beam epitaxy (MBE) specialists in Pennsylvania will provide their expertise under the Defense Advanced Research Project Agency s (DARPA s) "CERA" project, which kicked off in late July.
Led by Malibu-based HRL Laboratories and featuring Michael Fritze as its program manager, CERA stands for "carbon electronics for RF applications". The aim of the project is to develop a wafer-scale process for manufacturing graphene transistors that is compatible with a 200 mm silicon platform.
Discovered just four years ago by researchers at the UK s University of Manchester, graphene is a special form of carbon that exists as a single monolayer. It has some remarkable physical properties, one of which suggests that field-effect transistors (FETs) based on the material would operate ballistically "“ meaning that electrons would move directly from the source to the drain of the transistor without scattering.
So, as Jeong-sun Moon, one of HRL s senior researchers on the project, notes, graphene transistors could means much faster chips: "Technology based on a graphene-on-silicon platform could revolutionize a number of military applications," he said.
"This new generation of transistors will provide the military community with better than state-of-the-art RF components that have unprecedented capabilities."
Although the graphene transistors could, in theory, operate much more quickly than either silicon or III-V FETs, there is still a major question mark over whether such devices could be manufactured on a commercial scale.
The four-year CERA effort is designed to show whether or not that is possible, and is split into three phases. The first of these will concentrate on new processes for creating thin-films of graphene, with possible methods including SiC-based thermalization, CVD and MBE.
HRL says that it will use an "innovative carbon MBE process" that has been developed in-house to deposit single crystalline layers of graphene onto a silicon substrate.
If it proves possible to generate these films, the next stage will focus on increasing the deposition area to a 100 mm-diameter silicon wafer, controlling the graphene thickness with greater precision, and making initial transistors.
And if all that goes to plan, stage three will see transistor performance optimized and a shift to 200 mm wafers that ought to be compatible with high-volume manufacturing processes.
By the time that the project ends in September 2012, DARPA hopes to have demonstrated a W-band low-noise amplifier to validate the transistor performance, and anticipates applications of graphene in imaging, radar and communications modules.