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Imec develops strained germanium based FinFETs

The firm's replacement process on 300mm silicon wafers envisages a possible evolution of the FinFET/trigate architecture for 7 and 5nm CMOS technologies

At the IEDM 2013 conference, imec reported the first functional strained germanium quantum-well channel pMOS FinFETs, fabricated with a silicon Fin replacement process on 300mm silicon wafers.

The device shows a possible evolution of the FinFET/trigate architecture for 7nm and 5nm CMOS technologies.

Since the 90nm technology, embedded SiGe source/drain has been a popular stressor method to produce strained Si that enhances pMOS devices. With diminishing device dimensions, the volume to implement stressors in the source and drain has also been severely scaled.

Especially, with thin-body devices like FinFETs, the difficulty is even more pronounced. A possible relief would be to implement highly-strained material directly into the channel itself.

Imec’s solution, growing compressively strained germanium channels on a relaxed SiGe buffer, has already proven to boost the channel mobility, and is also known for its excellent scalability potential.

The use of a Fin replacement process to fabricate the strained germanium channel device makes it especially attractive for co-integration with other devices on a common silicon substrate.

The reported strained germanium p-channel FinFETs on SiGe trench buffer achieved peak transconductance (gmSAT) values of 1.3mS/µm at VDS of 0.5V with good short channel control down to 60nm gate length. The transconductance to subthreshold slope ratio of the devices (gmSAT/SSSAT) is high compared to published relaxed germanium FinFET devices.

Future developments will focus on improving the device performance through p-doping in the SiGe, optimising silicon cap passivation thickness on the germanium, and improving the gate wrap of the channel. 

“Unlike published germanium FinFETs, this work demonstrates a Ge-SiGe heterostructure-based quantum-well device in a FinFET form, which not only provides strain benefits but also- enhancesshort-channel control,” says Nadine Collaert, program manager of the Ge/IIIV device R&D. 

“Just recently, we reported the implementation of IIIV material into the device architecture using a fin replacement process,” states Aaron Thean, director of the logic R&D program at imec. “This new achievement, implementing germanium into the channel through our fin replacement process, is another key ingredient to our menu of process possibilities for monolithic heterogeneous integration to extend CMOS and SOCs.”

Imec’s research into next-generation FinFETs is part of its core CMOS program, in cooperation with key partners including Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba/Sandisk, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia and Xilinx.

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