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Better buffers for III-Vs-on-silicon

A two-step buffer based on GaAs and InP creates a foundation for quantum well structures with very high mobility

The researchers grew four heterostructures, featuring different channel and barrier designs, as well as differences in delta-doping. Structure (d) produced the highest mobility.

Engineers at Hong Kong University of Science and Technology have advanced the development of III-V-on silicon devices by inventing a buffer technology with a relatively high thermal conductivity.

Their work could aid the development of III-V-on silicon heterostructures, which are attracting much interest because they could help to maintain the march of Moore’s law – they could allow the silicon channels in transistors to be replaced with III-V material sporting a higher mobility.

One attraction of this switch in channel material is a reduction in power consumption, which results from a fall in the operating voltage of the IC without compromising the transistor’s current. Reduced IC power consumption is highly valued: It cuts cooling requirements and can extend the battery life of mobile devices. 

Forming high-quality III-V epistructures on silicon is not easy because these two types of material have an 8 percent lattice mismatch, significant differences in thermal expansion coefficients and different crystal polarities. Due to these differences, III-V layers can be riddled with defects that degrade device performance.

However, if engineers turn to sophisticated buffer structures, they can grow high-quality layers. This approach, which has been pioneered by a team including engineers from IQE, has shown that a ternary buffer allows the formation of InAlAs quantum wells with a mobility as high as equivalent wells grown on lattice-matched InP. The downside, however, is the relatively poor thermal conductivity of the III-V ternary alloys.
Kei May Lau, who leads the group at Hong Kong University of Science and Technology, has addressed this with binary buffers of InP and GaAs: “They have a ten-to twelve times better conductivity than indium aluminium arsenide.” Encouragingly, the quality of the devices grown on these structures appears to be similar to those grown on InP, according to sheet resistance measurements at various temperatures.

Lau and her co-workers produced their high-mobility quantum well structures on 100 mm p-type silicon (111) substrates, which were chemical-cleaned prior to loading in an Aixtron AIX-200/4 low-pressure MOCVD reactor. Before growth, the substrate was heated to 800 °C and annealed for 30 minutes at 100 mbar in hydrogen gas. This step removed any remaining native oxides and promoted the formation of double steps on the silicon surface.

Growth of the epistructure began with deposition of a GaAs nucleation layer between 390 °C and 420 °C, followed by the addition of a 0.5-1.0 mm-thick GaAs buffer, while temperature was ramped from 550 °C to 630 °C. On this the researchers deposited an InP layer at 450 °C, plus another InP layer at 630 °C. The latter featured a 10 nm-thick interlayer of In0.58Ga0.42As that led to dislocation bending and surface smoothing.

Cleaving the epiwafer into quarters enabled evaluation of four different In0.52As0.48As/InxGa1-xAs  (x≥0.53) heterostructures (see figure for details).

Insights into how to optimise buffer quality were provided by atomic force microscopy and transmission electron microscopy (TEM). The former revealed that the nucleation temperature plays a critical role in self-annihilation of antiphase domain boundaries and the elimination of deep pinholes on the GaAs surface. 410 °C is the sweet spot, leading to atomic-step flow and a root-mean-square roughness of just 1.1 nm over a 5 mm by 5mm scan area.

Meanwhile, TEM revealed the high density of dislocations at the GaAs/silicon and the InP/GaAs interface, which both arise due to 4 percent lattice mismatch. The good news, however, is that many defects vanish after intersecting with one another in the buffer layer, and the In0.58Ga0.42As interlayer in the InP buffer prevents some dislocations propagating into the upper active layers.

Of the four samples, heterostructure D, produces the highest mobilities:

10,080 cm-2 V-1 s-1 at 300K and 39,600 cm-2 V-1 s-1 at 77K. These values led to a sheet resistance of just 157 Ω/¨ at 300K, and 48 Ω/¨ at 300K.

It is not yet clear whether a trimming of the buffer thickness is required to make it suitable for transistor production − but it may already be suitable for photonics.

“Photonic devices do not have a similar demand, as integration on silicon photonics is yet to be well defined,” comments Lau. “We have reported both normal-incidence and edge-waveguide-coupled photodetectors grown on similar InP/GaAs/silicon buffers, and the buffer thickness does not seem to be a concern.”

Ref: Q. Li et. al.

Appl. Phys. Express 7045502 (2014)

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