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IBM develops way to integrate III-V materials on silicon

Template-assisted selective epitaxy (TASE) could be a way to extend Moore's Law, say researchers

Scanning electron microscope images of single crystal structures made using template-assisted selective epitaxy (silicon is in green, and the compound semiconductor in red)

A team of IBM researchers in Zurich, Switzerland with support from colleagues in Yorktown Heights, New York has developed a process for growing compound semiconductor crystals that will allow them be integrated onto silicon wafers. 

Appearing this week in the journal Applied Physics Letters, from AIP Publishing, the work may allow an extension to Moore's Law, according to the researchers. "The whole semiconductor industry wants to keep Moore's Law going. We need better performing transistors as we continue down-scaling, and transistors based on silicon won't give us improvements anymore," said Heinz Schmid, a researcher with IBM Research Zurich and the lead author on the paper.

The IBM team fabricated single crystal nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires, made with III"“V semiconductors  (InAs, InGaAs, GaAs).

The new crystals were grown using an approach called template-assisted selective epitaxy (TASE) using MOCVD. This approach allowed them to lithographically define oxide templates and fill them via epitaxy, in the end making nanowires, cross junctions, nanostructures containing constrictions and 3D stacked nanowires using the already established scaled processes of silicon technology.

According to the researchers, the benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400"‰cm2/V"‰s, while the alongside fabricated InAs MuG-FETs with ten 55"‰nm wide, 23"‰nm thick, and 390"‰nm long channels exhibit an on current of 660"‰Î¼A/μm and a peak transconductance of 1.0 mS/μm at VDS"‰="‰0.5"‰V. 

"What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology," said Schmid. "Importantly the method is also economically viable."  

He added that more development will be required to achieve the same control over performance in III-V devices as currently exists for silicon. But the new method is the key to actually integrating the stacked materials on the silicon platform, Schmid said.

"˜Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si' by H. Schmid et al, Appl. Phys. Lett. 106, 233101 (2015)

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