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Nanowire FETs For Future Logic

To maintain the march of Moore's law, silicon foundries may introduce germanium and III-V nanowire FETs at the 5 nm node

I BET THAT before you shut the front door, you check that you have your essential items with you. Keys? Yes. Wallet? Yes. Smartphone?

If you have forgotten the latter, it's back inside to hunt for it. And I suggest that you head first for the charger, as there is a good chance that it'll be hooked up there, getting the juice that it needs to last through the day.

This scenario illustrates our love-hate relationship with our mobiles. We cherish them for providing us with entertainment and communication on the go, but are frustrated by battery levels that plummet far too fast. 

So, if the makers of smartphones are going to tempt us to splash out on a new model with superior capability, this replacement must not compromise battery life. And that means that its microprocessor must draw no more power than its predecessor, while packing a greater punch, in terms of computing power, thanks to an increase in transistor count.

Since the birth of the silicon industry, increases in IC transistor count have been driven by the introduction of smaller devices consuming less power. Miniaturisation of the transistor has enabled it to operate at a lower voltage, which is a big deal, because active power has a quadratic dependence on the operating voltage. 

Unfortunately, it is getting ever harder to reduce the voltage of the silicon MOFSET while maintaining its performance. This impending roadblock has motivated an interest in alternative devices, which feature channels sporting higher mobility materials, such as germanium and the III-Vs. These devices can operate at lower voltages than silicon equivalents, while maintaining their performance.

A great place to find out about the latest developments in non-silicon MOSFETs is the International Electron Devices Meeting (IEDM). Held most-recently in Washington on 7-9 December 2015, delegates at this meeting got to hear about a variety of novel nanowire FETs with the potential to succeed the latest generation of silicon MOSFETs, which are three-dimensional devices with a protruding fin. At IEDM imec reported its latest results with InGaAs nanowire nFETs; Peide Ye from Purdue announced the fabrication of a CMOS inverter from germanium nanowire pFETs and nFETs; and a group from Singapore revealed how to make III-V nanowire pFETs and nFETs on a substrate sporting an incredibly thin buffer layer.

As a developer of finFETs and silicon and non-silicon nanowire FETs, the European microelectronics centre imec is in a great position to evaluate the prospects for all these technologies. 

Discussing this in an interview with Compound Semiconductor magazine, Vice-President of Logic at imec, Aaron Thean, said that he expects the silicon finFET to be the dominant technology at the 10 nm node, and also at the 7 nm node, where there might be an introduction of a SiGe channel. "Beyond that, we are out of knobs," explained Thean, arguing that the "˜electrostatics' degrade, leading to a hike in leakage current. "It turns out that with the tri-gate structures, the top gate does have electrostatic control "“ but the taller the fin, the further [the gate] is from the bottom of the fin."

To improve electrostatics at the 5 nm node, the device architecture must move to a nanowire transistor "“ with this design, the gate wraps all around the channel. Researchers at imec are already evaluating the capability of silicon nanowire transistors, as well as variants incorporating III-Vs for the nFETs and germanium for the pFETs. In all cases, efforts include the development of a high-yield manufacturing process that can churn out reliable circuits incorporating p-type and n-type devices in the world's leading foundries.

If these chipmakers are to switch to alternative channel materials in the 2020s, processes will have to be developed that enable device production on silicon substrates with diameters of 300 mm or more. And this is challenging, because there are significant differences between the atomic spacing found in crystalline silicon and that of the alternative channel materials. Due to these differences, when a III-V or germanium is deposited directly on a silicon substrate, strain builds up in the epilayer that leads to device-destroying defects.

At imec, researchers have been working for several years to develop a technology for forming high-quality III-V and germanium devices on silicon substrates. Progress led to the development of a process for making finFETs with non-silicon channels, and this now forms the basis for the production of nanowire transistors.

Fabrication begins by forming trenches in a widely available form of silicon wafer that features shallow trench isolation. With this form of engineered substrate, there are trenches made from silicon, separated by regions of silicon dioxide. The silicon is etched away to create trenches that have V-shaped grooves at the bottom. Depositing InP in these furrows leads to the creation of defects, due to the 8 percent lattice mismatch with silicon. However, the defects âˆ' missing planes of atoms aligned at about 45 degrees to the wafer surface âˆ' terminate at the trench walls, enabling the growth of high-quality material near the wafer surface.

InGaAs is grown on top of the InP column, before the latter is removed. Following fabrication of a gate stack, nanowire FETs are formed with a gate length of 50 nm. 

The imec-led team produced InGaAs nanowire FETs by growing material in trenches with a V-shaped bottom, and then etching material.

In 2014, the team reported early results with this process in the journal Electron Device Letters. Since then, improvements have been made to the gate stack, thanks to a strong collaboration with ASM. 

Niamh Waldron, a Principal Engineer at imec, and lead-author of the paper describing this work at IEDM, believes that the latest devices represent a major breakthrough, because the performance of these III-V transistors is as good as those made on native substrates.

What makes this result even more impressive is that it has been realised on a 300 mm line, using foundry tools. "You are always more worried about process damage, defects in the epi, and whether you can get there in the end," says Waldron.

Her claim of a nanowire MOSFET performance that is equal to that of III-V devices is based on a figure for gate transconductance, which reflects the mobility in the channel. In imec's devices, this is 2200 µS/µm for an operating voltage of 0.5 V, which is about two-thirds of the voltage used in circuits made with Intel's 14 nm finFET process.

Another important figure-of-merit for the transistor is its sub-threshold swing. This assesses the quality of the transition between the on-state and the off-state.

The value of the sub-threshold swing plays a critical role in attempts to reduce the operating voltage for the circuit, so that its power consumption falls. If the supply voltage is reduced while the threshold voltage is kept constant, this cuts the current flowing through the device. The obvious way to address this is to trim both the supply voltage and the threshold voltage, but cutting the latter increases leakage. What is actually needed is to introduce devices with a steeper sub-threshold swing, because this allows transistors to operate at a lower threshold voltage while producing the same level of leakage.

For a MOSFET, carrier statistics govern the lowest possible value for the sub-threshold swing: it is 60 mV/decade. For the imec device, the sub-threshold swing is significantly above this, at 110 mV/decade. So, if these devices are to be used in ICs, this value will have to come down. This should not prove too tricky, however, as in 2014, in Electron Device Letters, the team reported 4 nm InGaAs nanowires with a sub-threshold swing of about 65 mV/decade. "But we didn't get the on-performance," says Waldron. "It's all about getting good on-performance and the off-state. This is where we have to start thinking outside the box for good passivation, so we can achieve both at the same time."

Thean believes that at the 5 nm node and below, if III-V and germanium nanowire FETs are introduced in foundries, they will not completely replace those made from silicon. Instead, he expects all three devices to co-exist, due to concerns relating to leakage currents: "Anything that is 10 nA and below is very difficult to get with germanium or the III-Vs, and its hard to imagine that people will not care about leakage in the future."


Peide Ye's team has developed processes to form germanium nanowire nFETs and pFETs, and used this to make inverter circuits.

An all III-V approach

Pioneering an approach with III-V nFETs and III-V pFETs is a collaboration between at team led by Yeo Yee-Chia and Gong Xiao at the National University of Singapore (NUS) and Yoon Soon-Fatt's group Nanyang Technological University (NTU). 

"InGaAs is a promising material for nFETs, however it is not suitable for pFETs, because it has a very low hole mobility," says Gong Xiao from NUS. "So we needed another material for the pFET. In this work, we used GaSb, which has a higher hole mobility."

To form these transistors on silicon, engineers insert a buffer structure between the devices and the substrate. This approach is well known, but the buffer used by the Singapore team is much thinner than usual: it is just 150 nm-thick, compared to a typical value of around 1 µm.

Another strong feature of this work is the architecture of the MOSFET. According to Xiao, if a single nanowire were used to replace a fin, the current that would be delivered would be compromised, due to the reduction in the volume of charge-carrying material. "That's why the nanowires have to be stacked, in order to deliver a high current within a certain footprint. In this work, we not only realised the InAs nFET together with the GaSb pFET, we made both of them vertically stacked." 

Development of the thin buffer technology, which enables significant cost savings associated with less material usage and a higher tool throughput, took place in Yoon Soon-Fatt's group. Here, they started with a 6° offcut germanium-on-insulator wafer with a silicon base and deposited, via MBE, a 70 nm-thick layer of GaAs, followed by a 50 nm-thick layer of GaSb.

"Under proper growth technology, dangling bonds will form at every fourteenth gallium atom site, to accommodate the large lattice mismatch between GaAs and GaSb," explains Xiao. Defects that result from dangling gallium bonds are confined to the interface, while high-quality material is present 10 nm away from this.

The team produced nanowire FETs from these wafers. Operating at 0.5 V, a pFET and an nFET with a channel length of 500 nm and 20 nm produced a sub-threshold swing of 188 mV/decade and 126 mV/decade, respectively. Values for transconductance were not reported. 

Vertically stacking nanowires, an approach pursued by researchers from Singapore, enables an increase in current density from the footprint of the device.

It is not surprising that the device results need to be improved, as this work is still in its infancy. Xiao says that there are plans to: refine the gate stack, which should lead to an increase in the drive current; and to work with better epiwafers. The first devices were made with wafers with a 2.6 nm surface roughness, but recently the team from NTU improved its growth process, leading to a reduction in roughness to 0.5 nm. "In future we will use these wafers to do device fabrication," says Xiao.

High-resolution transmission electron microscopy reveals how interfacial misfit defects can address the issue of strain resulting from the growth of III-Vs onto germanium films.

Switching to germanium

Choosing the right material for the nFET and pFET is a dilemma that Ye has mulled over for a long time. He has been working with III-V transistors for the last 15 years, and has recently expanded his research effort to encompass devices made from germanium, which is an easier material to process 

With germanium, it's easy to make a pFET "“ and much, much harder to make an nFET. There are issues associated with Fermi-level pinning that make it very challenging to produce a good n-type contact. 

"Two-and-a-half years ago, one of my PhD students took a very, very simple approach "“ he tried to make the n-contact using a high doping concentration," explains Ye. "All of a sudden we moved the current one order of magnitude higher than anyone else."

This accomplishment provided the springboard for the first CMOS process for a planar device, followed by the first finFET with germanium CMOS, and now, announced at the recent IEDM, the first nanowire-based germanium CMOS. With this technology, sub-threshold swing for the nFET is just 64 mV/decade, and transconductance is 1057 µS/µm. Combining this with a pFET enabled the fabrication of an inverter circuit, operating at 1 V, that produced a maximum voltage gain of 54 V/V. Ye claims that this gain is close to that delivered by state-of-the-art silicon nanowire CMOS inverters, and says that he hopes to reduce the operating voltage of his circuits to 0.5 V.

High-resolution transmission electron microscopy reveals how interfacial misfit defects can address the issue of strain resulting from the growth of III-Vs onto germanium films.
Before Ye's germanium FETs could be introduced in foundries, their dimensions would need to shrink "“ but not by that much. For example, the width of the nanowires would only need to reduce from 10 nm to about 6 nm, if they were to be introduced at the 7 nm node.

One appealing aspect of Ye's process is that it does not require epitaxial steps. His team uses 200 mm wafers made by Soitec, which feature insulating and germanium layers on a silicon substrate. There is nothing to stop the production of 300 mm variants for processing in the world's leading foundries.

A noteworthy difference between the process used at Purdue and that suitable for high-volume production is associated with the lithography step. The university team uses electron-beam lithography, rather than a self-alignment technique, and this leads to higher capacitances, which prevent measurements of the speed of the circuit.

In contrast, at imec all work is conducted with foundry tools, speeding the path from development to a manufacturing-ready process. Here, one of the biggest concerns for researchers working on III-V FETs is whether the defect level is sufficiently low.

"We have proved that the defectivity of our devices is quite good already," says Thean. "But it is still not completely clear that it is sufficient for a very dense circuit of the future." Efforts will be directed at developing superior techniques for measuring and quantifying defects, and evaluating the relationships between defects and device and circuit yield.

Before III-Vs and germanium nanowire FETs are produced in silicon foundries, there also needs to be an introduction of suitable processing equipment for epitaxial growth and passivation steps. 

With the introduction of the 5 nm node around five years away, progress will have to be fast if non-silicon nanowires are to make an impact. But even if these devices miss this boat, they could still be a commercial success. "If you could co-integrate with silicon, you could do RF and other applications," reasons Thean.

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