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TUNNEL FETs: The Key To Greener Microprocessors

Increasing the indium content in the InGaAs channel boosts the drive current of a tunnel FET while maintaining its great switching behaviour
BY ALIREZA ALIAN AND AARON THEAN FROM IMEC

If the silicon industry keeps pace with Moore's law, the state-of-the-art microprocessors of the 2020s will contain hundreds of billions of transistors packed onto a chip no bigger than a postage stamp. This is a staggering hike in transistor count since the birth of the IC, taking their number to a level that is comparable to that of neurons in the human brain.

However, due to circuit energy dissipation and power budget constraints, it may not be possible to switch all the transistors most of the time. Instead, much of the silicon may remain dark "“ that is, not all the devices can switch together at once due to power limits, so a lot of them should remain off while only part of them are operational at any given time. The solution is the introduction of a more energy-efficient switch.


Atom probe tomography reveals the position of atoms. Here it is used to study an InP vertical structure grown on silicon. The technique uncovers atomic-level defects in III-Vs decorated by germanium diffusion. 

The origin of substandard efficiency is an inherent weakness of the MOSFET, the workhorse switch for the chips of today. This class of transistor forms a far from ideal switch, with a steepness of switching action "“ known as the sub-threshold swing "“ that is quite far from abrupt. 

Making matters worse, the sub-threshold swing deteriorates with scaling, because as the gate and channel get shorter, there is diminishing control of electrons via the field-effect. Unwanted consequences result, including increased leakage and challenges that arise that are associated with lowering the operating voltage, which is needed to cut the power-consumption per transistor. 
To address all these issues, the silicon industry has switched from a single-gated planar transistor to a double-gated vertical MOSFET that is also known as a FinFET. This move to a three-dimensional device architecture has delivered two significant benefits: it has improved the sub-threshold swing; and it has enabled the chip's operating voltage to drop below 1 V while maintaining its performance [1].

Another merit of the switch from a planar device to a FinFET has been a trimming of transistor leakage. This move to "˜greener' transistors must continue, because chip power non-scalability is becoming by far the biggest concern surrounding the future for energy-conscious electronics [2,3].

The MOSFET limit

For the regular MOSFET, there is a fundamental limit to the sub-threshold swing "“ at room-temperature, it can't fall below 60 mV/decade (at this value, changing current by a decade requires a 60 mV shift in gate voltage). Far lower sub-threshold swings can be reached, however, by moving to different classes of transistor, including the tunnel FET(TFET) (see Figure 1).

Figure 1. TFET operation for an n-type device with a p-type source and an n-type drain. The gate voltage in the off state is such that the tunnelling distance, L, is large, and no current flows through the device. A positive gate voltage bends the bands in the channel, shrinking the tunnelling distance L. This allows tunnelling to start and current to flow. The doping in the source is usually high because this creates a steeper band bending in the on state and boosts the current, thanks to a narrower tunnelling distance L. A smaller bandgap trims the tunnelling barrier height, while a higher mobility means lighter carriers. These modifications increase the tunnelling rate and consequently boost the drive current. Note that Ec and Ev denote conduction and valence band edges respectively. 

Many research groups have fabricated this form of transistor. There has been some success to date, including a demonstration of steep switching in a silicon-based TFET [4]. However, no reports have emerged of a circuit made with these devices.

To date, the steeper swing in the TFET comes at the expense of a low drive current, which is exacerbated when the device is operated below 0.5 V. To address this, the tunnelling resistance has to be trimmed while increasing gate action as much as possible, so that these devices can switch at reasonably fast speeds.

Success on this front requires the introduction of a new semiconductor material. The ideal candidate has to combine a high mobility and small bandgap, because this will deliver a hike in drive current via an increase in the tunnelling rate, which governs current capacity. Amongst the options for improving the TFET, the compound semiconductor material system offers great potential.

Unfortunately, turning promise into a reality is far from simple. For starters, it is far more challenging to process and build III-V devices than it is to make them with the more mature silicon CMOS material systems. And making the situation even harder, on top of the many challenges of designing and engineering III-Vs, TFETs are fundamentally more sensitive to material defects. These imperfections in the crystal lattice result from broken atomic bonds, which may exist in the form of extended line structures that span regions in the crystals and create electron traps. These imperfections may occur at interfaces between different materials, or in the bulk volume of the device "“ and they may be occurring naturally, or induced during device processing.

A major drawback of these imperfections is that they lead to trap-assisted-tunnelling, which hampers a steep sub-threshold swing. This tunnelling process "“ occurring in parallel with the favourable direct band-to-band tunnelling process "“ takes place at the tunnelling junction, which is located at the source-channel junction (see Figure 2). The implication is that the performance of the TFET is governed by the quality of the source-channel junction and its local interface with the gate oxide.

Figure 2. Trap-assisted tunnelling: In an ideal TFET, as shown in figure 1, electrons only tunnel directly from one band to another; however, in the presence of traps within the bandgap and in the tunnelling region, electrons can be thermally excited into the trap and then tunnel into the conduction band (note that the inverse is also possible, such as tunnelling into a trap and thermal excitation into the band). This has a detrimental impact on the sub-threshold swing, because it creates a parallel parasitic current that destroys steep switching. Since the process involves thermal excitation into a trap, it is strongly temperature dependent, which means in the presence of a significant amount of trap-assisted tunnelling, the sub-threshold behaviour of the current-voltage characteristics will be significantly changed with temperature, as demonstrated in figure 5. 

Trap-assisted-tunnelling has been a significant impediment to realizing steep switching in all forms of TFET. Its signature is a variation in the device's input characteristics "“ that is, the change in drain current with gate voltage at a range of temperatures "“ when the transistor is operated above the off-state leakage current. When trap-assisted-tunnelling is absent, these characteristics are almost temperature independent; but when they are there, the variations with temperature are easy to spot (see Figure 3).


Figure 3. The temperature-dependence of current-voltage can expose trap-assisted tunnelling. The graph on the left shows a simulation of TFET behaviour without trap-assisted tunnelling. The device behaviour above the leakage floor is temperature independent. The leakage floor is dominated by the Shockley-Read-Hall process, so it is strongly temperature dependent (see Noguchi et. al. , IEDM 2013, for an example of experimental device behaviour of this kind). The graph on the right shows a simulation of the TFET behaviour with trap-assisted tunnelling. The behaviour varies significantly with temperature, which is the signature of substantial trap-assisted tunnelling.

In late 2013, a group from the University of Tokyo reported a breakthrough in InGaAs TFET performance. They produced negligible trap-assisted-tunnelling, thanks to a novel approach for fabricating the source of the device, where tunnelling takes place [5]. The source is formed by diffusing zinc from zinc-doped spin-on-glass. Note that the use of zinc is common, as it is widely used for p-doping InGaAs layers. In the case of the TFET, zinc diffusion creates a highly p-doped source, and a clean source-channel junction with low defectivity.

One downside of the work by the Tokyo team is that their device had other weaknesses. Despite negligible trap-assisted-tunnelling, their device is still not able to produce sub-threshold swing below 60 mV/dec, possibly due to non-optimized design or other non-idealities.

Increasing indium

Our team at imec are admirers of the work of this group from Tokyo. We are using the zinc diffusion process for our study of III-V TFETs, because we believe that this p-doping process is the most promising way to date to realize negligible trap-assisted-tunnelling in this class of devices.

To increase the TFET's drive current, which is its Achilles heel, we have made two modifications: we have introduced a 8 nm-thick In0.7Ga0.3 As layer in the channel, and we have developed a self-aligned diffusion process to trim the gate-source overlap (see Figure 4). 

Figure 4. Increasing the indium content in the channel from 53 percent to 70 percent improves device performance. Experimental details, as well as the process flow, can be found in [6]. 


Figure 5. Activation energy varies with gate voltage. The plot is obtained from measurements of current-voltage at temperatures from 77K to 400K. In the off state, the activation energy is around half the bandgap "“ this is the signature of a Shockley-Read-Hall-dominant process. The low activation energy is advantageous, leading to low variations with temperature. This is a signature of dominance of a band-to-band-tunnelling process. A sharp transition step from band-to-band-tunnelling to Shockley-Read-Hall processes reveals that there is little trap-assisted tunnelling. Also shown is an example of a silicon-based device with a significant amount of trapassisted tunnelling, characterized by a gradual transition between the two processes.

The device that results produces very little trap-assisted-tunnelling. This is seen in the small variations with temperature of the device's input characteristics above its off-state leakage current (see Figure 3 for simulations of drain current as a function of gate voltage at various temperatures, and Figure 5 for extracted values of activation energy, based on this data).

A very pleasing aspect of our work is the significant hike in drive current that results from the insertion of the In0.7Ga0.3As layer. We attribute this gain to a combination of a higher mobility, a smaller bandgap material in the channel and an increase in carrier confinement (see Figure 6). Carrier confinement is partly aided by a favourable band alignment between In0.53Ga0.47As and In0.7Ga0.3As, and it also gets a helping hand from the thin thickness of the In0.7Ga0.3As channel. 

Figure 6. Simulations of In0.53Ga0.47As and In0.7Ga0.3As double-gate TFETs with different channel thicknesses. The smaller band gap, as well as the confinement in the 8 nm channel, improves device performance. The impact of the confinement is significantly stronger than the bandgap. 

The sub-threshold swing of our transistors is similar to those produced by the Tokyo group, and does not penetrate the sub 60 mV/dec barrier. However, the combination of a sub-threshold swing approaching 60 mV/dec and a high drive current positions our In0.7Ga0.3As  quantum-well channel TFET as one of the very best devices of its kind (see Figure 7 for a comparison of its performance to that of other leading tunnel FETs). 

A stumbling block to producing all III-V MOS devices is the realisation of a reliable gate stack. Despite decades of work, there is yet to be a report of clear success. Operation of a TFET is markedly different from that of a MOSFET, making it interesting to compare the reliability of both classes of device, when they sport identical gate stacks. Intuitively, if gate stacks are identical, both devices should be similar, in terms of reliability and in the physics associated with charging and discharging.

Measurements confirm this hypothesis. Both classes of device produce similar shifts in threshold voltage with stress voltage and duration, implying that they have similar lifetimes. Differences are noted, however, when comparing the degree of degradation of sub-threshold swing as a function of the induced threshold voltage shift (caused by stressing the device). With the TFET, this degradation is slower than it is with the MOSFET (see Figure 8). This is an interesting observation, given that the kinetics of the oxide trapping and de-trapping are identical in both classes of transistor.

To understand the origin of this variation, we have studied plots of capacitance and current, both as a function of voltage (see Figure 9). The graphs offer a valuable insight into device behaviour: despite the similar flat band voltages, which are clear from the plots of capacitance as a function of voltage, the threshold voltages of the two devices differ significantly. It is the TFET that has a much higher threshold voltage than the MOSFET. 



Figure 7. Benchmarking of imec's In0.7Ga0.3As  TFET to other reported III-V TFETs reveals that the performance of its device approaches that of the best reported heterojunction III-V TFET. Ion is extracted assuming a Vdd of 0.5 V and at Ioff of 100 pA/ mm "“ these are values that are relevant for low standby power applications. Where the target Ioff level was not reached, Id-Vg was extrapolated. Where available, a Vd of 0.5 V was used "“ otherwise it was 0.3 V. The impact of Vd on Ion is not significant, except for [12] where the data point for Vd is 1 V.

Figure 8. The sub-threshold swing of the TFET degrades far less than that of the MOSFET for the same amount of positive-bias, temperature-instability-induced threshold voltage shift (ΔVth). An explanation for this is provided in figure 9.

Figure 9. Despite having similar flatband voltages (shown by the grey area), the TFET has a significantly larger threshold voltage than the MOSFET. In terms of the operating energy range, this implies that the TFET operates close to the conduction band edge and inside the conduction band, while MOSFET operation starts from about midgap. In other words, the TFET operates over a significantly narrower energy band than the MOSFET. This means that the TFET is less sensitive to interface states at the midgap, which are usually large in III-V devices. Another consequence is that the TFET interacts with a smaller proportion of traps inside the gate oxide (border traps), thanks to its smaller operating energy range. This latter is believed to be the reason for the slower degradation in sub-threshold swing in the TFET, as observed in figure 8.

Based on this insight, and considering the equivalent operating energy range in the band structure, it can be concluded that the operating energy range of the TFET is much narrower than that of the MOSFET. While the TFET operates at/inside the conduction band edge, the MOSFET operates over the full upper-half of the bandgap, as well as inside the conduction band. A key consequence of this is that the range of border trap energy levels interacting with channel charges during the current-voltage sweep is more limited with a TFET, so is less prone to degradation of the sub-threshold swing. Another implication of the difference in the operating bandgap energy ranges of the two classes of transistor is that the TFET operates away from the mid-bandgap of InGaAs. This is an advantage, because the interface state density is usually high around the mid-bandgap of InGaAs.



Figure 10. Moving from a homojunction to heterojunction TFET increases drive current, but can also result in a hike in sub-threshold swing.

Our observations to date suggest that the TFET has the same lifetime, measured in the form of time-to-failure, as the MOSFET. However, its strength is its superior immunity to interface traps at midgap, which historically plague III-Vs.

To make TFETs more appealing, there is a need to address their biggest weakness "“ the low drive current. One option is to turn to a heterojunction. However, with this modification, gains in current are so far at the expense of an inferior sub-threshold swing (see Figure 10). What's needed is to improve this substantially and get the sub-threshold swing to plummet to significantly below 60 mV/dec. This will be tough, but maybe it can be accomplished within a decade, and enable the TFET to become a worthy greener alternative to the MOSFET.




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