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Technical Insight

Magazine Feature
This article was originally featured in the edition:
2016 Issue IV

Wet Beats Dry In 3D Backside Process Study

With 3D integrated circuit wafer stacking entering mainstream HVM, backside processing has become a more critical step for device manufacturers. A study commissioned by Veeco Instruments points to clear advantages of wet etch processing. By Mark Andrews, technical contributor, Silicon Semiconductor.

For 3D-IC strategies to succeed, critical manufacturing processes need to maintain productivity and efficiency without extending costs and complexity to the point where negatives outweigh positives. A recent study commissioned by Veeco Instruments points to clear advantages for wet etch processes worthy of consideration by manufacturers looking for ways to optimize performance while reducing factory floor space and overall costs.

Careful and highly precise backside processing is an area of 3D-IC production that manufacturers pay particular attention to since success (or defects) have a multiplying effect. Backside processing is so important since through-silicon vias (TSVs) finished during these and subsequent steps are hands-down favorites for creating interconnects. TSVs also provide the greatest number of interconnection points compared to other strategies and can be produced with mature, cost-effective technologies.

While there are various points along the production process where TSVs can be made (first, middle or last,) the so-called "˜via-middle' position has emerged as the most favored for etching vias into silicon. This point is somewhere between the contact and BEOL layers; approaches may differ from one manufacturer to another. (See Figure 1) In via-middle processing, the wafer has been bonded to a carrier and has gone through an initial grinding to thin the bulk of the silicon wafer.

Process tool manufacturers have focused on the steps that actually reveal the vias as a point of differentiation since the two major approaches are quite different and choices at this point represent options to reduce costs and complexity while improving results.

The figures and details documented in the study referenced in this article were produced by SavanSys Solutions LLC in cooperation with Veeco Instruments. SavanSys is a group of respected and specialized semiconductor industry supply chain cost modeling analysts that use the company's patented software and extensive process flow library to create activity-based cost models for assembly and/or fabrication plant operations.

Two primary approaches to TSV reveal

After mechanically grinding silicon to remove the bulk of unneeded material, additional thinning is required to safely reveal the vias. This takes place to eliminate surface roughness and any defective silicon that may have been released during grinding. The final etch and surface conditioning can be done with a combination of chemical-mechanical planarization (CMP) and plasma dry etching, or wet chemical etching. One approach that is not typically used is simple CMP as a solo step due to the potential for contamination if copper particles come into contact with the silicon wafer backside.

CMP or dry-etch processes utilize costly slurries and involve cleaning steps to remove slurry particles and other contaminants not used in wet etch. They also include expensive plasma equipment and etching gases with much higher consumable and maintenance costs. Plasma etch processes also require a separate wet cleaning following intermediary steps. The SavanSys researchers found that Veeco's wet etch equipment and processes could replace four tools commonly used in the dry etch process of record (POR) including the CMP, plasma etch, cleaning and silicon thickness measurement tools. The key to making the wet etch approach most economical is eliminating the CMP step in the overall sequence. They found that Veeco's two-step wet process (all performed inside one advanced WaferEtch® tool,) accomplishes this in a simpler, more cost-effective manner.

Accelerating production/cutting costs

How can the wet etch approach to TSV reveal involve fewer steps and yield better results while it cuts costs? Essentially, the tool and processes were built from the ground up to do all these things along with delivering greater flexibility. Veeco Vice President of Marketing for its Precision Surface Processing BU, Scott Kroeger, explained the genesis of their wet etch approach.

"We were focused on the fact that the industry needs a lower cost silicon etch-to-reveal process in order to help the industry scale. The current competitive solution involves multiple tools, so the Capex associated with that is significantly higher than a single tool solution like Veeco's. Also, we were focused on delivering excellent surface (condition) and uniformity with lower consumables cost, which is also critical to enabling the silicon etch process. One other very important criteria in the design approach was to build a system that could sense incoming wafer profiles and adjust the etch process automatically to compensate without operator intervention. This takes complexity out of the process recipe tuning and puts the system virtually into autopilot," he remarked.

The first step in Veeco's wet processes relies on a high-rate silicon etch to contour and smooth the silicon surface to within ~2µm of the TSVs. This step eliminates grind marks from previous processing and compensates for non-uniformities in the silicon wafer. Next, the chemistry is changed to SACHEM Reveal Etch to precisely uncover the vias since this etchant is selective to silicon and does not etch the oxide liner covering the TSVs. Etching is controlled by integrated measurement of the silicon wafer before and after using the company's Profile Match Technology™ (PMT). (See Figure 2)

It should be noted that PMT adds utility beyond establishing and controlling etch rate. The incoming silicon thickness is measured and the program determines the etch profile based on TSV depth data and the reveal height requested by the manufacturer. This ability to precisely and automatically control thickness requirements enables compensation for radial variations for a more uniform reveal height, so it also reduces the amount of reveal needed in many cases. Lower reveal heights translate into lower passivation deposition, and typically, less final CMP to expose the copper surface.

Veeco's Chief Technical Officer for Precision Surface Processing, Laura Mauer, explained that the result of these key, primary wet etch process steps is a smoother wafer with fewer irregularities and a more precise approach to finished thicknesses.

Mauer noted that Veeco's new approach does not incorporate TMAH (tetramethyl ammonium hydroxide), an etchant that has been used by other companies and research groups. Veeco replaced TMAH with SACHEM Reveal Etch™.

"TMAH is considered toxic, especially in the high concentrations that are needed for silicon etching. We eliminated it when we invented our approach. Veeco utilizes SACHEM Reveal Etch, which is about 5 times less hazardous than TMAH. The chemistry is one part of the differences in processes. The other is that Veeco's process uses a two-step etch sequence. First, a fast etch smooths the surface followed by the second step using the SACHEM etch to selectively thin the silicon and safely reveal the TSVs," she said.

Another important benefit of Veeco's wet etch compared to a dry etch is the final product: reduced surface roughness along with precisely controlled TSV reveal. While post-processing surface roughness can be 4nm or higher with dry etch, Mauer indicated that Veeco's wet etch pushes the benchmark below 4nm.

Cost modeling

Researchers utilized activity-based cost modeling to understand key cost centers of the TSV reveal process with both etching methods. This is a bottoms-up approach that involves breaking down a process flow into individual activities with the costs associated with each item factored into determining how dry vs. wet etch compare on an equal footing. For comparison sake, the TSV reveal process using dry etch begins with bonding to a carrier wafer. The process moves through a series of grinding and CMP steps occurring before and after dry etch, and includes chemical vapor deposition (CVD) passivation once the vias are revealed, along with a few metrology steps. The wet etch reveal process also begins with bonding to a carrier wafer and then proceeds through two major liquid-based process steps within one machine.

Figure 3 shows the cost comparison between the standard four-tool process of record versus Veeco's wet etch process. It is understood that this percentage is heavily dependent on design parameters, type of assembly, the number of redistribution layers (RDLs), etc. However, even with many variables it is clear that TSV-related processes are costly "“ about 11 percent of the total. Since every factory is somewhat different these numbers may vary; however, the comparison provides insight about relative cost structures and equipment needs as well as materials costs. Yields were assumed to be equal while any potential defect reductions obtained would add to the cost benefits. Determining the baseline is based upon the dry etch POR.

Strikingly, we can see that the two-step wet etch reveal approach delivers the same serviceability as the five-step dry etch baseline processes, yet wet etch costs less than half as much. Secondly, this type of comparison easily identifies where cost is coming from within each incremental step and not just the overall costs. Within the baseline dry etch POR, the plasma etch stage contributes high capital cost while the CMP step contributes high material cost. In the wet etch approach, most of the cost is associated with equipment (roughly 80 percent), which is not surprising since one tool essentially replaces four tools required for TSV reveal in the current POR that includes CMP, dry etch, clean and metrology. The charts in Figure 4a and 4b demonstrate how TSV reveal step costs change as the etch rate changes.

Comparing baseline cost drivers for both etch approaches provides important insights. Cost of ownership is critical to ensuring that an investment like TSV reveal is contributing to a manufacturer's competitiveness and not holding it back. Veeco's Scott Kroeger said that besides reducing the number of tools a factory needs to maintain, his company's approach also delivers better performance and increases throughput, reducing capital costs as well as consumable expenses. The Veeco approach also has long term applicability to a wide range of current and future device form factors.

"The TSV reveal configuration of our WaferEtch tool is well suited for other silicon etch process applications beyond 3D-IC. One main driver for wafer thinning is to reduce the thickness of semiconductor packages such as fan-out wafer level packaging for use in consumer electronic applications, MEMS devices and image sensors.

"There is a growing need for ultra-thin wafers (below 120µm) and we believe that wet etching can achieve the best results in terms of uniformity and reducing surface roughness. Also, we find that after mechanical grinding and polishing steps, there is subsurface damage in the wafers that causes significant stress and presents a potential for yield loss. We have demonstrated that our wet etch process can remove most of the sub-surface damage and strengthen the wafers," he added.

Better control, smaller footprint, lower costs

The SavanSys analysis of Veeco's wet etch approach to wafer thinning and TSV reveal shows that wet etch can outperform various dry etch processes while reducing the complexity of these critical steps. Since TSV reveal can amount to 11 percent of an interposer-based process like those employed in building 3D-IC devices, controlling costs here has a multiplier effect and direct impact on a manufacturer's bottom line. By choosing an advanced wet etch tool like the Veeco WaferEtch solution, manufacturers can reduce the number of tools they have to maintain as well as the volume of costly consumables while achieving superior performance. Manufacturers can also extend their capabilities into additional wafer thinning operations that are expected to take a larger role in supporting next-generation device designs.

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