Making A Debut: The P-type SiC MOSFET
Breaking new ground with SiC MOSFETs that are p-type, rather than n-type, swells the promise for the future of complementary inverters
BY JUNJIE AN, MASAKI NAMAI, MIKIKO TANABE, DAI OKAMOTO, HIROSHI YANO AND NORIYUKI IWAMURO FROM THE UNIVERSITY OF TSUKUBA
SiC is renowned for its wide band gap and large dielectric constant. These assets help SiC power devices to have the upper hand over silicon in many regards, including: a lower on-state resistance; a higher maximum operating temperature; a lower conduction loss; and a smaller increase in chip temperature during operation, thanks to the high thermal conductivity.
The weaknesses of silicon devices limit the efficiency of some circuits, and hold back the capability of others. When they are deployed in conventional inverters, they are highly problematic. In these circuits, where p-type and n-type transistors are paired together, there is the potential for a short circuit to arise from the on-state of both devices. To prevent this, engineers must ensure that the dead time, corresponding to the delay time of the gate driver circuit, is at least 1.0 ms. However, addressing that problem introduces another: a relatively high total harmonic distortion in the output AC waveforms. This is highly undesirable, because it makes it very challenging to increase switching frequency – and this is wanted, because it holds the key to smaller, lighter, more efficient inverters.
Figure 1. The cross-section of the SiC p-MOSFET fabricated at Tsukuba University. The inset shows the wafer of the fabricated SiC p-MOSFET.
Our device is a descendent of an implantation and epitaxial MOSFET developed by the National Institution of Advanced Industrial Science and Technology. It has a vertical structure (see Figure 1), and its fabrication involves n-channel implantation.
The foundation for our p-MOSFET is a silicon-face, p-type 4H-SiC substrate with the thickness of 350 mm and resistivity of 2 Ωcm. On this we deposit a 5 mm-thick drift layer with a doping concentration of 1.6×1016 cm-3. The bottom of the n-channel region is formed with selective implantation of nitrogen ions at a concentration of 4×1018 cm-3. On this surface we grow a 0.5 mm-thick n-channel region with doping concentration of 5×1015 cm-3.
Our p-MOSFET features a JFET region, formed by selective aluminum ion implantation that reduces resistance. After adding this, the steps to complete device fabrication are: the addition of a 50 nm-thick gate oxidation layer on the surface; formation of the gate electrode, via the deposition and annealing of highly-doped polycrystalline silicon; and the creation of source and drain electrodes with a metal process. With this process we form 3 mm by 3 mm p-MOSFET die.
Electrical measurements on our p-MOSFETs reveal a typical threshold voltage of -5.32 V and a breakdown voltage in excess of -730 V (see Figure 2). A weakness of this transistor is its on-resistance, which is more than ten times that of the n-channel equivalent, due to the combination of a low hole mobility in the bulk and channel, the thick p+ substrate and the conventional gate oxidation process. We are not too concerned with this high on-resistance, however, because we believe it could plummet by: adopting an advanced cell design, such as super-junction; and turning to a trench gate structure and state-of-the-art fabrication technologies.
Figure 2. The typical on-state, blocking characteristics for the fabricated SiC p-MOSFET.
We have focused on evaluating the short circuit capability of the SiC p-MOSFET via measurements of drain current and gate voltage as a function of short circuit withstand time. These experiments, which involved using a -300 V DC bus, show that the gate voltage can be as high as -27 V, with a short-circuit withstand time ranging from 75 ms to 90 ms (see Figure 3 (a) and (b)). Destructive failure with this testing methodology takes place at 90 ms, and the associated short circuit energy is 16.1 J cm-2. Note that there are no signs of degradation of the gate voltage, despite an electric field as high as 5.4 MV/cm being applied to the gate oxide.
To evaluate our p-MOSFET, we have compared it to a SiC n-MOSFET with a 2.8 mm by 2.8 mm die size, a drift thickness of 8 mm, and a rated voltage of 650 V. Again, we evaluated short circuit capability with measurements of drain current and gate voltage, but this time we used a maximum short-circuit withstand time of just 26 ms (see Figure 3 (c) and (d)). With this device, the short circuit energy is just 13.7 J cm-2, so approximately 85 percent of the energy for the SiC p-MOSFET. Our p-MOSFET also has the upper hand over the SiC n-MOSFET in gate voltage stability, with the later gradually decreasing by 4.1 V.
Figure 3. Experimental results of the time dependence of the drain current waveforms, and gate voltage for SiC p-MOSFET and SiC n-MOSFET, respectively.
We have shorted the gate and source terminals in these p-type and n-type MOSFETs by applying a high electric field to the gate oxide and using an elevated junction temperature. In both devices, almost no damage or degradation is observed in the p-n junction, thanks to an infinite impedance between the two terminals. Even when the gate-source terminals are completely shorted, devices retain their blocking characteristic.
Simulations have enabled us to investigate the reliability of the p-n junction and the gate oxide during short circuit transients. Results show that when using a 300 V DC bus, the electric field in the gate oxide gradually increases until meeting its maximum value, at which point the device gradually switches from its off to its on-state (see Figure 4).
This existence of a high electric field, which will occur at a high surface temperature, highlights the need for ruggedness between the gate and source terminals. This field is to blame for the degradation in the gate voltage from 27 V to 22.9 V in the SiC n-MOSFET (see Figure 3 (d)). Thanks to the larger effective barrier height between SiC and SiO2 for pMOS than nMOS devices – it is 3.05 eV, rather than 2.70 eV – our SiC p-MOSFET can effectively avoid degradation until it reaches the critical failure condition.
Figure 4. Simulation results of electric field profiles in the gate oxide at four points of short circuit transient in Figure 3(a) and (c) for SiC MOSFETs with gate oxidation layer of 50 nm
Our device also outperforms the SiC n-MOSFET in terms of gate leakage. Using a -500 V DC bus and considering a short-circuit transient, our device shows no gate current, while it is 1.2 A for the n-type device (see Figure 5). We have also investigated impactionization. Armed with data from the short circuit test results, simulations show that in both devices impact ionization peaks at the junction corner (see Figure 6). The hole impact ionization in the SiC p-MOSFET is higher than the electron impact ionization in the SiC n-MOSFET, but its value of less than 1×1012 cm-3 s-1 indicates that it is too small to induce avalanche breakdown.
Figure 5. (a) Energy band diagrams of 4H-SiC and SiO2 illustrating barrier heights. (b) Experimental results of gate leakage current with 500 DC bus for the fabricated SiC p-MOSFET and the SiC n-MOSFET.
Figure 6. Simulated results of impact ionization for the SiC MOSFETs in the X and Y cutline.
To confirm the avalanche immunity of our p-MOSFET, we have measured its short-circuit capability, using a drain voltage of -500 V (see Figure 7). This experiment shows that the device can successfully survive high avalanche conditions – the short circuit energy is 15.7 J cm-2, and short circuit withstand time is 58 ms. Our measurements and simulations demonstrate that our p-MOSFET is capable of withstanding severe shorts circuits, thanks to the ruggedness of its p-n junction and gate oxide. Compared to the n-MOSFET, our p-type device delivers a 15 percent higher tolerance for the short-circuit energy, and a higher gate oxide reliability and avalanche immunity during the short-circuit test. What’s more, our p-MOSFET promises to have a higher safe-operating area than its n-type sibling.
These results are very encouraging for the future of complementary inverter circuits based on pairs of SiC p-type and n-type MOSFETs.
Part of this work has been implemented under a joint research project of Tsukuba Power Electronics Constellations (TPEC).
Figure 7. Experimental results of the time dependence of drain current, gate and drain voltage waveforms for a SiC p-MOSFET with maximum short circuit withstand time of 58 μs and -500 V DC bus.