Transphorm To Preview PFC Reference Design At EPE'17 ECCE Europe
First look at next generation development tool kicks off four days of education about high-voltage GaN design techniques and testing
High voltage GaN power chip company Transphorm will be at the EPE'17 ECCE Europe show in Warsaw, Poland, September 11 to 14 showing the company's new reference design and discussing reliability testing.
At the show it will preview 3.3kW Bridgeless Totem-Pole Power Factor Correction reference design, built on the company's next generation (Gen-III) 650V 35mÎ© GaN FET. The board uses DSP firmware to deliver a turnkey design solution with no code expertise required. The reference design targets engineers building high-efficiency applications for automotive on-board chargers and industrial power supplies.
The company will also be speaking on 'Reliability Testing of High-voltage GaN FETs' In addition to applying industry standard qualification tests (i.e., JEDEC and AEC-Q101) to GaN devices, aggressive lifetime testing is required to establish operating life expectancy. Accelerated stress tests, such as high voltage off state and high temperature DC current tests, are used to determine activation energies and acceleration factors which can be used to estimate operating life for any given mission profile. Jim Honea,senior manager of applications engineering, will provide an overview of test results and typical application of them during Transphorm's EPE vendor session.
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