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Scrutinising Traps In SiC MOSFETs

Simple approach highlights the benefits of nitridation

Researchers in Japan are pioneering a new, simple approach to quantifying traps at the SiO2/SiC interface of the SiC MOSFET.

Lead author of the paper detailing the work, Tetsuo Hatakeyama from the Advanced Power Electronics Research Centre at Tsukuba, says that this effort is motivated by the urgent need to address weaknesses at the SiO2/SiC interface, which is the most important part of the SiC MOSFET.

The performance of this device is held back by a high MOS channel resistance, resulting from the low mobility at the SiO2/SiC interface. A high density of traps at the interface is probably the root cause of this weakness.

Measuring the density of traps at interfaces is normally accomplished by high-low capacitance-voltage measurements. But this is not suitable for the oxide-semiconductor interface in SiC MOSFETs.

When making high-low capacitance-voltage measurements of any device, it is assumed that traps only respond to low frequencies, and are not influenced by the high frequencies, typically 100 kHz to 1 MHz. However, that's not the case with SiC MOSFETs. "They respond to the high frequency, because of the low excitation density to the conduction band," explains Hatakeyama. The upshot is an underestimate of the density of traps near the edge of the conduction band of this SiC MOSFET.

To address this weakness, Hatakeyama and his colleagues, working with researchers at the University of Tsukuba, have developed an approach based on the combination of Hall measurements and split capacitance-voltage measurements. With the later, the capacitance of the gate is split into a source-gate component, and a gate-substrate component.

Post-oxidation annealing of SiC MOSFETs in nitric oxide for either 60 minutes or 120 minutes leads to a substantial reduction in the density of interface traps.

"In the case of the split-CV method, one terminal is connected to the gate electrode," explains Hatakeyama. "The other terminal is connected to the source or drain, or both. The substrate is grounded."

To determine the trap density with the approach of Hatakeyama and co-workers, the first step is to measure the free carrier density as a function of gate voltage with Hall effect measurements. After this, the split-CV method determines the capacitance between the gate and channel as a function of gate voltage. Integrating this reveals the total density of carriers at the interface induced by the gate voltage. The trapped carrier density is given by taking this figure for the total density of carriers at the interface, and subtracting the free carrier density, which has been given by Hall measurements. Via calculation, the density of interface traps near the conduction band is known.

The Japanese team has used its technique to determine the effect of nitridation on the density of interface states in SiC MOSFETs. Nitridation is a common method for improving this interface "“ it is used by the likes of Wolfspeed, Rohm, ST and Mitsubishi. Working with devices that have a thermally grown oxide with a thickness of 50 nm, the team annealed one sample in nitric oxide for 10 minutes, another for 60 minutes, and a third for 120 minutes. A non-annealed device acted as the control.

Measurements of field effect mobility highlighted the benefits of nitridation, with the best result, a value of nearly 40 cm2 V-1 s-1, coming from a sample undergoing treatment for 60 minutes. Note, however, that this mobility is far less than that for bulk 4H SiC, which is typically 1000 cm2 V-1 s-1. Dividing the free carrier density by the total carrier density gives the free carrier ratio, which increased from 4 percent to 30 percent with nitridation. However, even 30 percent is a low figure, which may partially account for the far lower mobility at the SiO2/SiC interface compared to bulk SiC.

Calculations show that nitridation enables a 75 percent reduction in the density of interface states at 0.1 eV below the conduction band (see Figure). However, this density is still in excess of 1013 cm-2 eV-1.

Hatakeyama and co-workers are now planning to characterise SiO2/SiC interfaces in a variety of SiC MOSFETs, in the hope that this will uncover a technique for improving this critical part of the device.



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