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ENTRY: Hybrid InGaAs/SiGe CMOS Circuits

Scientists at IBM Research GmbH achieved the first demonstration of an InGaAs/SiGe CMOS technology on Si substrate using processes suitable for high-volume manufacturing on 300 mm wafers. InGaAs/SiGe hybrid integration is the main path to enable further improvement of power/performance trade off metrics for digital technologies beyond the 7 nm node. Based on selective epitaxy their approach yielded functional inverters and dense arrays of 6T-SRAMs the basic blocks of digital CMOS circuits.

This work, first of a kind,was previously presented at a recent VLSI Technology conference. It concludes a series of key demonstrations for InGaAs/SiGe CMOS reported in multiple contributions and highlights for the last four years at IEDM meetings and VLSI Technology Symposia. Since many years the technological bottleneck is to demonstrate a path that enable simultaneously the growth of defect-free InGaAs the fabrication of high performance InGaAs field effect transistors "on-insulator" and their co-processing with SiGe devices all on a silicon substrate. A few approaches have been proposed but the work nominated is the only one that reports basic building blocks of digital circuits at relevant dimensions and achieves a major milestone towards a manufacturable hybrid InGaAs/SiGe CMOS technology. It features in a single technology the selective growth of high quality InGaAs-on-Insulator regions, and the fabrication of InGaAs finFETs with physical gate length Lg= 35 nm and good device characteristics and the processing of functional 6T-SRAM cells with a cell area ≈0.4mm2.

All metrics compare favourably to industrial state-of-the-art numbers (e.g. ≈0.1mm2 for an SRAM cells in 22 nm technology). It clearly highlights the potential of the nominated work as the method of choice to co-integrate InGaAs and SiGe MOSFETs for advanced CMOS technology. It also opens the door towards future low cost RF or photonic circuits based on a similar hybrid III-V silicon technologies.



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