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This article was originally featured in the magazine:
Volume 23 Issue 6

Lighting Up Silicon With Quantum Dots

News

InAs quantum dots lasers are ideal for silicon photonics: they draw very little power, take up very little space, and can operate over a wide temperature range

BY JUSTIN NORMAN, DAEHWAN JUNG, YATING WAN, ARTHUR GOSSARD AND JOHN BOWERS FROM UCSB

Quantum dot lasers have a great deal of promise, and are getting better all the time. Thanks to this, they are tipped to revolutionize silicon photonics and optical technologies by enabling the scalable manufacture of densely integrated photonic systems on a single chip.

Merits of the quantum dot laser include its small form factor, low power consumption, and multi-functionality. These attributes have great appeal, and could allow this laser to serve in various applications, including: datacentre and high-performance computing interconnects; chemical and bio-sensors for medical diagnostics; leak detection; and security purposes, in highly precise, GPS-free navigation systems.






Table 1. The cost of native substrates for laser growth is far higher than that for silicon, while size is more limited.

All these opportunities arise through the absence of an efficient silicon light source for silicon photonics. This material is plagued by an indirect bandgap, making it a poor light emitter. Despite much effort, researchers are yet to produce an electrically injected silicon laser delivering continuous-wave output at room temperature.

Getting III-Vs onto the chip

Today, engineers within the silicon photonics community address this weakness through the heterogeneous integration of III-V materials. This includes the growth of laser materials on III-V substrates, followed by bonding to patterned silicon-on-insulator (SOI) substrates. CMOS processes turn the bonded material into laser cavities, which are aligned with silicon waveguides in the SOI active layer. The light that is generated by the quantum dot laser is evanescently coupled into the waveguide, and routed to other photonic components.

One of the strengths of this approach is that it can yield complex photonic integrated circuits with hundreds of high-performance, on-chip components. However, there are downsides: manufacturing scalability is limited; bonding adds complexity; and as the III-V substrates used for laser growth are removed and discarded after bonding, this adds significantly to production costs (see Table 1 for details).








Figure 1. Plan-view transmission electron microscopy of GaAs grown on silicon. Red dots indicate threading dislocations. The inset, an atomic force microscopy image of a layer of InAs quantum dots, illustrates their relative density compared to dislocations.

A far better approach is to form the lasers via the direct growth of III-Vs on silicon. However, this is challenging, because the inherent mismatch in lattice constant between the two materials spawns a high density of threading dislocations, which propagate in the growth direction and act as non-radiative recombination centres, hindering laser performance.

In addition, two more obstacles must be addressed to enable a commercially viable performance from the quantum dot laser: the polarity mismatch between silicon and the III-Vs, which drives the formation of antiphase domains that act as extended planar defects; and a mismatch in the thermal expansion coefficients. The latter results in more defects, and imparts a residual strain as the wafer cools from the growth temperature to room temperature. Due to a hike in defects, degradation increases and device lifetime shortens.

Fortunately, it is possible to produce efficient III-Vs lasers on silicon by turning to InAs quantum dots. Devices incorporating these low-dimensional structures feature particle-in-a-box like carrier confinement, making them inherently tolerant to defects. As these charge carriers are confined within a plane and trapped by quantum dots, they don’t tend to diffuse to a defect, so non-radiative recombination diminishes. Note that the likelihood of trapping a carrier by a dot rather than a defect is very high: the dot density is typically 4-6×1010 cm-2, while defect density is no more than 108 cm-2 (see Figure 1 for an illustration of this concept).

Another attribute of the InAs quantum dot laser is its ability to span a very wide spectral range. Careful selection of the dots’ size and cladding composition allows sources to produce an emission wavelength from around 1 mm to 1.6 mm. This wide range enables devices to serve datacom and telecom applications.






Figure 2. Photoluminescence spectra of as-grown InGaAs quantum well (QW) and InAs quantum dot (QD) material on GaAs and silicon substrates. Switching from a native to a foreign substrate leads to significant degradation in material quality for the QWs.

The tremendous tolerance of the quantum dots to defects is highlighted in photoluminescence measurements of various structures on native and foreign substrates. While the dots grown on silicon do not deliver the intensity they would do on a native substrate, they emit far more light than wells grown on the same foundation (see Figure 2). The recombination characteristics are so good that they can be used to make high output power lasers with low thresholds. In comparison, devices made from quantum wells grown on silicon fail to lase.

While defects don’t prevent the lasing of quantum dot lasers, their presence is still undesired. They do impact lasing performance by impairing material quality, and they should be managed as far as possible in III-V nucleation and buffer layers deposited on the silicon substrate.

Historically, the heteroepitaxial growth of III-Vs on silicon has been undertaken on planar (100) silicon with a 2-6° miscut in the surface orientation toward the [111] direction. This geometry is favoured, because it makes the formation of double atomic steps on the silicon surface energetically favourable. This inhibits antiphase domain formation and improves material quality. However, there is a significant downside: the miscut silicon is incompatible with the CMOS platform, preventing wafers formed in this manner from enjoying the manufacturing advantages needed to drive silicon photonics.

A two-pronged attack

To address this weakness, our team at the University of California, Santa Barbara, has started to develop growth techniques for III-Vs on CMOS-compatible, on-axis (001) silicon. Working in partnership with researchers at other universities, we have pioneered two different approaches: the use of a 45 nm GaP-on-silicon template for the regrowth of GaAs; and the patterning of silicon with {111} v-groove trenches, followed by the direct growth of GaAs, which coalesces to form a smooth GaAs-on-silicon template. Both approaches, and the success they have delivered, are discussed in the remainder of this article.

For the first of these two approaches, Minjoo Larry Lee’s group at the University of Illinois at Urbana-Champaign has pioneered the initial development of GaAs/GaP/silicon. Our role has been to continue this work.

Efforts with this GaP-on-silicon template make use of a highly developed process developed by NAsPIII/V GmbH of Marburg, Germany. The technology is based on the growth, by MOCVD, of nearly lattice matched GaP on silicon. By carefully controlling the silicon surface preparation and nucleation conditions, uniform, smooth, defect-free GaP-on-silicon can be realised across a full 300 mm wafer with a GaP thickness of only 45 nm.








Figure 3. The growth procedure for producing GaAs on a v-groove silicon (GoVS) template.

We and our colleagues have used these commercial, engineered substrates as the foundation for MBE growth of InAs quantum dot lasers. With the antiphase domain issue solved at the GaP/silicon interface, we only have to contend with dislocations arising from lattice mismatch between GaAs and GaP. Threading dislocations densities of 3×108 cm-2 have been realised in our lasers, with performances detailed in the scientific literature. By refining the growth conditions and introducing dislocation filtering layers, dislocations can be far lower – now they are down to 6×106 cm-2, and even lower values may follow as further optimization is in progress. A point of reference is the threading dislocation densities in commercial III-V substrates: it is typically of the order of 104 cm-2.

The other approach that we are pursuing – growth of GaAs on v-grooved silicon – is being undertaken through a collaboration with Kei May Lau’s group at the Hong Kong University of Science and Technology (HKUST). With this approach, the primary benefits are that the v-groove {111} surfaces suppress antiphase domain formation and it relaxes the strained GaAs material, largely through stacking fault formation, without generating high threading dislocation densities.

Proceeding in this manner, 300 mm CMOS-compatible silicon wafers are patterned with oxide delineated trenches 90 nm wide, separated by 40 nm SiO2 stripes (see Figure 3). These wafers are diced, etched in potassium hydroxide to create crystallographic {111} v-grooves, and loaded into an MOCVD chamber for the regrowth of GaAs, which forms nanowires. Following ex-situ removal of the oxide, further growth of GaAs causes nanowires to coalesce and yield smooth films. The inclusion of AlGaAs/GaAs superlattices smooths the film and filters defects, enabling higher material quality.

With this series of steps we have formed structures that have a dislocation density of 7×107 cm-2 in the final 1.5 mm of the film. Surface roughness, judged in terms of the root-mean-square value, is just 0.9 nm. As with the GaAs/GaP/silicon templates, growth conditions are refined day by day. Threading dislocation density has now fallen to the low 107 cm-2 range, with a stacking fault density of 2×107 cm-2.






Figure 4. The laser epi structure, including the multilayer active region, and two III-V/silicon template designs


Quantum dot lasers emitting near the datacom wavelength of 1.3 mm have been grown and fabricated on templates just described. MBE growth forms the heterostructures, while standard CMOS-compatible etching, deposition, and lithography processes define the architecture.

One feature of our design is the use of top p-contact and bottom n-contact layers within an AlGaAs graded-index separate-confinement heterostructure, which provides optical and electronic confinement to the active region (see Figures 4 and 5). At the heart of these devices are multiple layers of InAs quantum dots within In0.15Ga0.85As quantum wells that assist in carrier capture.

We have produced a range of devices, including those with a narrow ridge, a broad area, and a micro-ring based laser cavity. Ridge lasers range from 2 mm to 50 mm in width and 500 mm to 3000 mm in length, while micro-rings combine outer diameters of 5 mm to 50 mm with widths of 2 mm to 7 mm. The micro-ring devices enter new territory by providing the first demonstration of micron-scale laser cavities in epitaxial material on silicon. Note that the ridge devices were fabricated on both of the III-V-on-silicon templates, but micro-rings were only fabricated on V-groove based substrates (see Table 2 for a summary of the template and epi design parameters, and Figure 6 for images of fabricated devices).

All of these devices can deliver continuous wave emission under electrical injection. For the ridge lasers on GaP/silicon, p-modulation doped active layers are incorporated to improve high-temperature performance. This comes at the cost of a higher threshold current.

We have fabricated and measured hundreds of devices, formed using the three designs and two templates (see Table 3 for a summary of the best lasing characteristics).

All devices have a low threshold current design. In ridge lasers they can be as little as 30 mA, while for a 5 mm micro-ring they can be a record-setting 0.6 mA. Note that the previous record for low threshold, held by our team for efforts in 2014 on miscut silicon, was 16 mA.

Ridge devices are capable of a single-facet output power in excess of 100 mW, and can produce continuous-wave lasing from the quantum dot ground state at temperatures of up to 80 °C. In comparison, micro-ring devices can achieve this feat up to 100 °C. Unfortunately, with this class of laser, an accurate output power cannot be extracted from the micro-ring without an additional out-coupling structure to guide the light. Instead, output powers have to be simply measured from what is scattered from the ring sidewalls into an adjacent integrating sphere. This is only a small fraction of the total scattered light.







Figure 5. The band diagram for laser material at zero-bias

If quantum dot lasers are to serve any practical application, they must combine high performance with high reliability. Fortunately, the signs are promising. Our devices formed on miscut silicon have demonstrated extrapolated lifetimes of more than 4,000 hours at 30 °C and a high current density of 1.1-1.2 kA cm-2. Far longer lifetimes of more than 100,000 hours have been determined in separate work at University College London, using the relaxed condition of 130 A cm-2.

While these results are very encouraging, the defect density for on-axis templates is still higher than it is with miscut silicon. So more work is needed to propel performance, so that these devices deliver a commercial lifetime of 10,000 hours at conditions relevant to a given application, such as operation at 80 °C for datacentre and high-performance computing applications. To put these requirements in perspective, the preliminary results for our ridge lasers on the GaP/silicon templates reveal a lifetime in the several hundred to 1,000 hour range at 30 °C, using a drive current of a few kA cm-2.

Given the combination of promising lifetimes, low threshold currents and high output powers, it is clear that epitaxial III-V materials and devices show significant promise for silicon photonics. Results to date by our team are ground-breaking, and they should continue to improve as our material gets better and better. Note that since obtaining these results, the defect density in the GaP/silicon template has fallen by nearly two orders of magnitude, while the v-grooved template is making similar progress. Spurring on performance improvement is continual refinement to laser designs at the device and epi level. This should lead to much lower threshold currents, higher output powers, and higher-temperature CW operation.






Figure 6. The structure of a Fabry-Pérot ridge laser (top left) and a micro-ring laser (top right). A top-down optical micrograph of ridge lasers on a chip (bottom left), and scanning electron microscope images of a ridge cross-section and top-down of a micro-ring laser with 5 µm radius (bottom middle and bottom right, respectively).





When ready, transfer of our technology to a manufacturing environment should be relatively easy, as we have obtained our results on CMOS-compatible 300 mm silicon substrates, diced to fit research-scale growth reactors, and undertaking processing of the laser material with standard CMOS lithography and etching techniques. We are confident that our small-footprint micro-ring structures can realise high integration densities, with coupling of these sources to waveguides with established silicon photonics designs. This will allow direct integration of our ground-breaking lasers with existing components and other epitaxial III-V devices.






Table 2. A comparison of the epi parameters for quantum dot lasers formed on GaP-on-silicon and on GaAs grown on v-groove silicon.






Table 3. Results for lasers formed on silicon are promising, with micro-ring lasers delivering ground-breaking threshold currents.





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