Improving SiC Epilayers
A six-inch single-wafer tool with high rotation speeds yields uniform, high-quality SiC epilayers by Yoshiaki Daigo, Hideki Ito and Shinichi Mitani from Nuflare Technology
Tremendous energy savings can result from a switch to more energy efficient power electronics. So great can those savings be that if the adoption of high-efficiency devices were to exceed 90 percent, it could cut consumption by as much as 25 percent. This would be great news for humanity, as it would trim carbon footprints and cut utility bills.
The key to introducing more efficient power electronics is to replace silicon devices with those made from wider bandgap materials. The most established alternatives are those made from SiC and GaN. To ensure their high performance, these devices must be manufactured using growth tools that yield uniform wafers that contain very low levels of defects.
At NuFlare of Japan we have developed a family of single-wafer CVD tools that do just that – the EPIREVO range. These tools employ single-wafer, high speed wafer-rotation technology and are capable of providing high-speed growth of silicon, GaN and SiC epilayers. In all cases, the epitaxial films have high in-wafer uniformity.
Recently, we have optimised the growth of epilayers on 6-inch 4H SiC using our EPIREVO S6 tool. It is designed to yield epilayers that combine a high level of uniformity, in terms of thickness and doping concentration, with minimal surface and crystalline defects [1, 2].
Our EPIREVO S6 contains: an upper gas inlet; a hot-wall; a rotation holder; and resistive heaters, positioned on the sides and the bottom of the chamber (see Figure 1). One feature of this tool is that the position of gas injection nozzles in the gas inlet can be adjusted. By fine-tuning them, it is possible to optimise the uniformity of both the thickness and the doping concentration of the epiwafers . Prior to growth, a wafer is loaded into the chamber by a fully automated robot.
Figure 1. The CVD chamber of the EPIREVO S6.
With our tool, growth is typically undertaken at 1600 °C, using a wafer rotation speed of 600 rpm, a growth pressure of 26.7 kPa, and a chlorine-to-silicon ratio of typically 10. The process gases used are: C3H8 (carbon-source), SiH4 (silicon source), H2 (carrier gas), N2 (dopant) and HCl (to suppress the formation of silicon-related clusters).
To minimize surface defects produced by our tool, we have investigated the influence of the rotation speed during the temperature ramping step. During this ramp, two of our samples, A and B, have a rotation speed of 50 rpm; and the other two, C and D, have a rotation speed of 300 rpm (see Figure 2).
Measurements of the surface defect density and inspection with an optical microscope image analysis tool reveal that the density of all forms of defect fall when faster wafer rotation speeds are used during the temperature ramping step (see Figure 3). The greatest of these reductions is associated with triangles, which are the majority of surface defects.
We also note that when a higher rotation speed is used during the temperature ramp, this shortens the length toward the step-flow direction of defects categorized as Down-Fall-triangles (DF-triangles) and triangles. This implies that a higher rotation speed should be employed during the temperature ramping, because it reduces the chances of DF capture on the wafer surface.
Figure 2. The rotation speed and temperature for initial process steps
Two well-known imperfections that exist within the crystal structure of 4H-SiC, rather than on the surface, are stacking faults and basal plane dislocations. The latter can be reduced by growing a highly n-doped buffer layer prior to the growth of a drift layer. We have adopted that approach, producing epiwafers that have a 9.5 μm-thick drift layer with an n-type doping level of 8 x 1015 cm-3 on a 0.5 μm-thick, highly doped buffer layer with an n-type doping level of 1 x 1018 cm-3. Doping levels of these buffer layers were the same, but grown with different ratios between the flow rates of SiH4 and C3H8.
Figure 3. Surface defect density and typical surface defects on four samples. A and B were formed using a wafer rotation speed of 50 rpm during the temperature ramp phase; for C and D the wafer rotation speed was 300 rpm. Small pits generating triangles are indicated by arrows.
To expose the stacking faults and basal plane dislocations, we use photoluminescence to scrutinise three samples, grown with different carbon-to-silicon ratios. This optical technique revealed that in all cases, the surface defect density is negligibly low compared with the crystal structure defect density. In addition, photoluminescence determined that lowering the carbon-to-silicon ratio can reduce basal plane dislocations in the drift layer. Take this approach, and the defect density can be as low as 0.75 cm-2, including DFs, triangles, DF-triangles, stacking faults and basal plane dislocations.
Figure 4. Summary of surface (a) and photoluminescence (b) defect densities of the SiC stacks with a highly n-doped buffer layer grown with different carbon-to-silicon ratios. The rotation speed during the temperature ramping was 600 rpm.
As expected, we have found that our tool’s growth rate is fairly proportional to its SiH4 flow. That’s good news, because it indicates a suppression of silicon-cluster formation, thanks to the introduction of HCl into SiH4 . Using this approach, we can achieve growth rates as high as about 1 μm/min.
By adjusting the position of the gas injection nozzles in the gas inlet, we have been able to fine-tune the distribution of the local gas phase concentration of SiH4 and C3H8 near the wafer surface, along the radial direction. This allows us to tune uniformity of thickness and doping concentration simultaneously, by optimizing the total carbon-to-silicon ratio.
We have realised a growth rate of 54.7 μm/h, with a uniformity of ±2.53 percent (1.75 percent (σ/mean). For doping, the concentration and its uniformity are 5.46 ×1015cm-3 ±3.24 percent (1.53 percent ( σ/mean).
These values, and the defect-related studies, show that our EPIREVO S6 is capable of producing very high quality films of SiC that will aid the makers of power electronic devices.