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This article was originally featured in the edition: Volume 24 Issue 5

Gaining An Edge With Nano-ridges

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Aspect ratio trapping enables the fabrication of nano-ridge lasers on silicon substrates by Bernardette Kunert, Robert Langer, Marianna Pantouvaki and Joris Van Campenhout from IMEC and Dries Van Thourhout from Ghent University

Maintaining the march of Moore’s law is getting more and more difficult. In recent times, it has required the introduction of novel geometries and esoteric materials, such as hafnium dioxide. And in the years that lie ahead, progress may hinge on the use of III-Vs – either as a material for adding on-chip RF-functionalities, or for providing a light source that speeds on-chip and chip-to-chip communication.

Requirements for the integration of III-V and silicon technologies are more complex than the realisation of good performance. It is essential that the process must also be cost-efficient and suitable for mass production. So, in other words, it must be scalable and compatible with existing IC technology.

The key to cost-efficient, scalable integration is the monolithic hetero-epitaxial growth of III-V layers directly on a silicon substrate. This approach is superior to that of bonding at the wafer, chip and die level. However, the challenge is to develop a technology that can accommodate the latticemismatch between silicon and the majority of the III-Vs. Dislocation defects will arise, due to strain, so they have to be controlled and restricted to a constrained area, to allow the active III-V device layers to be free from defects.


Figure 1. Cross-sectional, scanning electron micrograph images of cleaved GaAs nano-ridges. (a), (b) and (c) show GaAs nano-ridges on top of 100 nm, 40 nm and 20 nm wide oxide trenches, respectively. All structures were deposited in a single growth. (d) a tilted top-view scanning electron micrograph image of an nano-ridge array on top of 100 nm-wide trenches. Some of the images are modified and reprinted from B. Kunert et al. Appl. Phys. Lett. 109 091101 (2016) with the permission of AIP Publishing.

Nano-ridge engineering

At imec, we are trailblazing a unique approach to the integration of III-Vs with CMOS. We are pioneering nano-ridge engineering. It begins by depositing, by selective area growth, III-V material inside narrow oxide trenches that are formed on patterned 300 mm silicon substrates. Further growth of III-Vs creates nano-ridges.

This approach may appear esoteric, but it is not – it is compatible with standard processes used in the silicon CMOS industry. Patterning of silicon and its oxide is based on the shallow trench isolation process, and the growth of the III-Vs is by MOCVD.

The ingenuity of our approach is that the growth starts with the deposition of III-Vs in narrow trenches with a high aspect ratio – that is the height of the trench is far greater than its width. It’s a technique that is known as aspect ratio trapping (ART), and it is successful with many different hetero-material systems. The geometry of the trench results in a very efficient dislocation trapping at the oxide side walls. Misfit and threading dislocations are constrained towards the bottom of the trench, creating a top region that is free from dislocation defects (more details on how it works can be found in the box “The art of aspect ratio trapping").

Aspect ratio trapping is particularly beneficial when combined with trenches oriented along <110> directions of silicon. This allows the preparation of a V-shaped silicon surface with two {111} planes. When III-Vs nucleate on a {111} silicon surface, this plane prevents the formation of anti-phase domains, which are detrimental to device performance.

When selective area growth continues, dislocationfree III-V material grows out of the trench. Adjusting the MOCVD growth parameters alters the form of the nano-ridge. For example, growth conditions can be selected to broaden the nano-ridge and thus increase the volume of III-V material, which can provide a foundation for new device architectures.



Figure 2. Left: An illustration of aspect ratio trapping of threading dislocations in {111} planes. Middle: Cross-sectional scanning electron micrograph images of a box-shaped GaAs nano-ridge surface. Right: Annular bright-field scanning transmission electron microscopy (ABF STEM) of a GaAs nano-ridge in cross-section along the trench. The transmission electron microscopy sample volume is also indicated in the scanning electron micrograph image by the red-dashed line. The dark blurry lines in the ABF STEM image are threading dislocations, which are all trapped inside the trench. The V-shaped {111} silicon surface induces a Moiré pattern in the transmission electron microscopy image close to the GaAs-silicon interface.

We have formed box-shaped GaAs nano-ridges on top of 100 nm, 40 nm and 20 nm wide trenches (see Figure 1). This series of growths shows that the fundamental shape evolution is independent of trench size. Viewing these structures from above with a scanning electron microscope reveals that the nanoridges are of high quality and are highly uniform.

Our nano-ridge engineering also has great strength and flexibility. Adjusting the growth conditions enables the shape of the GaAs nano-ridge to be tuned to a tall rectangle, a triangle or various diamond-like shapes. Different structures result from selective manipulation of the growth rate hierarchy of the various nanoridge facets. It is the facets with high growth rate that disappear quickly, while those with a low growth rate define the shape of the nano-ridge (see box “Nanoridge engineering" for more details).

We are not the first to report the shape control of ridges. Others have announced homo-epitaxial selective-area growth of III-Vs on the micrometre scale – this is a fundamental feature of epitaxial growth. We break new ground by applying aspect ratio trapping to hetero-epitaxy of III-Vs on silicon, and realise astonishing control of nano-ridge formation on the nanometre scale.

The effectiveness of aspect ratio trapping is highlighted by images acquired by annular brightfield scanning transmission electron microscopy (see Figure 2). This technique reveals that threading dislocations, visible as dark blurry lines, are restricted to within the trench, while GaAs nano-ridge material, on top of the oxide pattern, is free from these imperfections.

We are currently exploring additional metrology techniques that may provide a better insight into defect statistics. To date, we have a very strong indication that dislocation trapping is extremely efficient in trenches with a width of 100 nm or less for 300 nm deep trenches. Nevertheless, along the nano-ridge length we can see planar defects, such as a micro twin every several micrometres. To eradicate these defects, we are devoting much effort to optimising the III-V nucleation and the pre-cleaning step for the trench-patterned wafer.



Figure 3. (a) Cross-section scanning electron micrograph images of InGaAs/GaAs nano-ridge lasers with an InGaP cap on top of 60 nm-wide trenches. (b) High-angle annular dark-field (HAADF) scanning transmission electron microscopy image of a nano-ridge laser sitting on a 100 nm-wide trench. c) Finite difference eigenmode simulation of the basic transverse electric (TE)-like mode, based on the dimensions of the nano-ridge laser shown in (b). Some of the images are modified and reprinted from Y. Shi et al Optica 4 1468 (2017).

Lasers on the edge

The combination of impressive uniformity of the nano-ridge lines, the smooth surface morphology and a ridge with a width of several hundred nanometres lends itself to the production of a nano-ridge laser, where the nano-ridge acts as an optical waveguide. Working in partnership with Ghent University, we have produced such a device. It features In0.2Ga0.8As/GaAs multi-quantum wells, grown compressively strained on top of the (001) nano-ridge facet; and a lattice-matched In0.49Ga0.51P cap layer, which surrounds the full nano-ridge, ensures carrier confinement and provides surface passivation.

Cross-sectional scanning electron microscopy imaging of our device layer stack, sitting on top of 60 nm-wide trenches, emphasises the impressive continuity from ridge to ridge (see Figure 3 (a)). The InGaP cap layer around the waveguide ridge is easy to identify, and it is possible to make out the positions of the quantum wells.

Greater detail is provided by high-angle annular dark-field scanning transmission electron microscopy. When this is used to image a nano-ridge laser on a 100 nm-wide trench each of its layers is clearly visible. The device also contains a GaPAs layer, which is explored for strain compensation and additional carrier confinement.

The art of aspect ratio trapping

III-VS AND SILICON are lattice-mismatched, so the growth of the former on the latter generates defects. However, these imperfections can be trapped with great efficiency by selective area growth in highly confined trenches oriented along <110> directions of silicon. The key is to use trenches that are far higher than they are wide.

When III-Vs are deposited on patterned silicon/SiO2 substrates, misfit and threading dislocations form during the growth to release strain. A typical relaxation mechanism is the nucleation of dislocation half-loops at the growth surface, which glide down towards the interface between the III-V and silicon to efficiently release the strain.

If the dislocation Burgers vector is based on a 60° misfit dislocation, the slip plane is a {111} plane. Hence, as the dislocation half-loops start to glide down along the {111} plane and extend in width, the two threading dislocation ‘arms’ hit the oxide sidewall and are trapped. This trapping mechanism is easy to follow when the {111} slip plane is perpendicular to the trench sidewalls.

The {111} slip plane can also be parallel to the sidewall. When that’s the case, the dislocation half-loop ‘arms’ finally hit the oxide wall as the trench gets filled due to the inclined angle of 54.7° of the {111} plane, so long as the aspect ratio of the trench – that is its height to width ratio – exceeds 1.43. As aspect ratios for trenches are far higher than this, all dislocation defects are fully trapped in both directions, so long as the relaxation process proceeds via threading dislocations gliding along {111} planes. Success hinges on enhancing pronounced dislocation nucleation close to the interface between the III-V and silicon, to ensure full strain release of the hetero-layer.

Note that stacking faults and micro twins, which are planar defects running in the <111> direction, are only trapped in {111} planes parallel to the sidewalls. Consequently, a planar defect that is running perpendicular to the sidewall could penetrate the full III-V structure. So, to prevent this from happening, planar defect formation has to be eradicated by optimising the growth conditions, the silicon surface pretreatment and the fabrication process for the trenches.