This article was originally featured in the edition: Volume 24 Issue 6

Increasing Switching Efficiencies With Vertical Transistors

GaN FETs featuring a thin unintentional doped GaN interlayer as the channel and an in-situ grown gate-dielectric can boost efficiency at the system level, thanks to a higher channel mobility and lower on-resistance. By Dong Ji and Srabanti Chowdhury from the University of California, Davis, and Chirag Gupta and Umesh Mishra from the University of California, Santa Barbara

Power converters are widely used in power electronic systems, where they convert one form of electrical energy to another. They are used to form rectifiers, which convert AC voltages to those that are DC; they create inverters that provide the DC to AC conversion; and they step up and down DC and AC voltages.

Due to the widespread use of power converters, any increase in the efficiency of power electronics can play a crucial role in reducing the global carbon footprint. Currently, two-fifths of all the energy that is consumed is first converted into electricity, and this figure may rise to three-fifths with increasing use of electric and plug-in hybrid vehicles and high-speed rail transportation. And by 2030, it is anticipated that as much as 80 percent of electrical energy will pass through power electronics between generation and consumption.

To help to increase the efficiency of power electronics, in 2014 ARPA-E launched a new programme called SWITCHES – it is short for Strategies for Wide Bandgap, Inexpensive Transistors for Controlling High-Efficiency Systems. This effort, involving five universities and nine companies, has focused on the development of 1.2 kV power transistors that have the potential to realize functional cost parity with silicon-based devices.

Our team from the University of California, Davis, and the University of California, Santa Barbara, has played its part in this programme. Our contribution has been the development of a novel device – an in-situ oxide, GaN interlayer based MOSFET – that sets a new benchmark for DC performance at 1.2 kV.

The power electronics revolution

Today silicon, in the form of the MOSFET and the IGBT, dominates the market for power semiconductor devices. However, this pair of incumbent transistors is reaching a performance plateau, and almost all improvements are incremental.

To reach a new level of performance for power switching, there needs to be an uptake in devices made from wide bandgap materials, such as GaN and SiC. Devices made from these materials are able to set a new benchmark for the trade-off between the breakdown voltage and the on-resistance (see Figure 1).

Figure 1. The tradeoff between the specific on-resistance (Ron,sp) and the breakdown voltage for silicon and it two leading challengers, SiC and GaN

For GaN, the first generation of power transistor is the HEMT. It sports a lateral geometry and takes advantage of a two-dimensional electron gas channel, introduced by the polarization of the AlGaN/GaN heterojunction. Thanks to the high electron density and high electron mobility in this channel, the GaN HEMT can combine operation at high power with an extremely low on-resistance.

Following two decades of development, the GaN HEMT has been commercialized, with devices offering blocking voltages of 650 V or less. The blocking voltage is held by depleting the lateral channel between the gate and drain electrodes. So, to realise higher blocking voltages, there has to be an increase in the gate-to-drain spacing. In addition, to achieve high output current, the device must be scaled up in width. However, as a result, the device area is then so large that it is impractical for any application requiring blocking voltages over 1 kV.

Vertical virtues

For higher voltages, a far better approach is to build a vertical device. With this architecture, the device holds the blocking voltage in the bulk of the material by depleting the drift region, and the peak electric field occurs in the bulk GaN. A merit of this approach is the elimination of surface-state related dispersion, realised without the need for any special field plating structure. Note that to scale the current and the voltage, there must be an increase in the gate width and the drift region thickness, respectively.

The vertical GaN transistor is capable of delivering a very impressive power-handling capability. It is possible for a single die to simultaneously realise blocking voltages in excess of 1 kV and currents of more than 100 A. Such a high level of performance makes the vertical GaN transistor a more economical and viable solution for high-voltage and high-current applications.

Figure 2. The development of vertical GaN FETs.

The development of vertical GaN transistors can be traced back to the launch of single-crystal GaN substrates. Following a few quiet years, vertical device research took off in 2007 (see Figure 2). Milestones include Avogy’s development of a vertical JFET, which offered paths towards commercialization. Trailblazing efforts from that era have helped to spur wider support for vertical GaN transistors, and encourage further development of this device.

Our contribution to this field is a modification to the design of the vertical GaN transistor that improves channel properties. In a conventional GaN trench MOSFET, the channel forms on the vertical etched p-GaN sidewall, where sidewall roughness, ionized impurity scattering and ex-situ gate-dielectric deposition can hamper the performance of the channel. We address these weaknesses by using MOCVD to grow, on the trench structure, a thin unintentionally doped GaN interlayer, followed by an in-situ dielectric (see Figure 3 and Table 1).

Figure 3. Cross-section profiles of the in-situ oxide, GaN interlayer based MOSFET and the conventional MOSFET.

These refinements improve performance. The thin GaN interlayer increases channel conductivity with normally-off behaviour. In turn, there is a higher channel conductivity, alongside an improved channel/oxide interface that results from our in-situ regrowth technology, and this leads to a lower and better dynamic on-resistance. Thanks to these improvements, there is an overall reduction in switching energy losses and a hike in device reliability. In addition, this form of FET is free from current collapse, which is caused by the surface states.

Improvements in performance have been revealed by measurements made on our in-situ oxide, GaN interlayer based MOSFETs. When providing normally-off behaviour, realised by using a threshold voltage of about 2 V, they offer the same breakdown voltage as trench MOSFETs.

Table 1. Comparison of the conventional MOSFET and the proposed in-situ oxide, GaN-interlayerbased MOSFET.

Adjustments to our device can increase its blocking voltage. Without edge termination, our in-situ oxide, GaN-interlayer-based MOSFET is capable of a breakdown voltage of between 700-1000 V and onresistances of just 2.5-3 mΩ cm2 – this is for normallyoff operation, realised by applying threshold voltages in the range of 1-3 V. Adding a field plate enhances off-state performance beyond 1 kV, and turning to a double field plated structure propels the breakdown voltage to 1.4 kV (for a threshold voltage of 4.7 V and an on-resistance of 2.2 mΩ cm2).

There is a hysteresis is associated with the in-situ channel interface and the oxide. When Al2O3 is used, the threshold voltage can shift by about 0.3 V. To reduce this, we have turned to AlSiO, a move that has slashed the threshold voltage shift to below 0.1 V and improved DC performance.

So that we can demonstrate the performance advantage provided by our device at the system level, we have developed a device-circuit hybrid model. This enables a comparison of a power electronics system that uses the GaN FET as the switch with variants that use silicon and SiC. Our effort is both important and worthwhile, as there are no commercial pieces of software for modelling GaN devices and evaluating switching characteristics.

With our hybrid model, one can start by simulating the device with a two-dimensional drift-diffusion model, and go on to study its characteristics in a circuit, where an evaluation of its switching performance is possible. This approach offers an inexpensive, accurate way to project and benchmark performance. Note that it can be extended to any GaN-based power transistor (see Figure 4 for a flowchart of the hybrid simulation developed at UC Davis).

Using this model, we found that our GaN FETs have more than 30 percent lower switching losses than conventional trench MOSFETs, enabling the system to be operated in megahertz range with over 90 percent efficiency.

We will now build on our success with 1.2 kV GaN FETs that deliver excellent DC performance. Our next step will be to use these devices to investigate switching and reliability behaviours.