Hybrid Bonding: Going For GOLD
Hybrid bonding provides attainable scaling for packaging of compound semiconductor devices in copper or gold
BY JOHN GHEKIERE FROM CLASSONE TECHNOLOGY
Fabricating semiconductor devices begins by growing epiwafers, with efforts directed at ensuring high-quality crystalline material with minimal imperfections. Once a device is completed, it often has to be integrated into its CMOS brain in order to carry out its impressive tasks. Commonly this integration is accomplished by employing advanced packaging techniques, many of which include some form of pillar formation and bonding. However, continued input/output (I/O) scaling is taking conventional packaging approaches and putting them out of reach for many manufacturers. Hybrid bonding offers abundant opportunity for I/O density scaling.
Increasing in popularity, heterogeneous direct bonding, also known as hybrid bonding, is a technology that involves directly bonding dielectric and interconnect features, either between two wafers, or between a chip and wafer. Such a concept is not new, having been studied and developed over the course of more than a decade, and already deployed in the manufacture of some CMOS image sensor devices. Yet, until recently hybrid bonding has not gained widespread traction as a viable approach for packaging integration. But that is changing.
The exponentially increasing technical difficulties associated with the scaling more well-established approaches, primarily based on pillars, has driven interest in hybrid bonding, along with a hike in its funding. The challenges of scaling that are facing leading-edge pillar applications are so great that they are putting enabling input/output density scaling out of the reach for most device manufacturers.
This limitation is a major blow for compound semiconductor device manufacturers operating in this highly competitive marketplace. As the majority of dollars spent on development are largely committed to true device technology, there is little funding left to try and advance an already profoundly advanced packaging flow. Adding to the woes of the compound semiconductor industry are the relatively small R&D budgets compared with those of the manufacturers of silicon-based devices. Foundries are an option, but as compound semiconductor devices are still largely produced on wafers with a diameter of 150 mm or less, finding a foundry operating at these wafer diameters and yet capable of such advanced packaging integration is becoming impossible.
Fortunately, hybrid bonding offers a genuine alternative. This approach is clearly important, justifying expenditure on development that should offer a great return. While some investment optimisation is valuable, there is the promises of multiple generations of incremental innovation, an attractive proposition compared with the diminishing returns that characterise further pillar development.
For pillar and bump packaging, a 10 mm by 10 mm ‘micro-pillar' represents the state of the art. To scale the pitch any further is challenging to even the most advanced manufacturers in the industry. Progress on this front would allow an increase in the number of inputs and outputs on a device - realising this requires increasing the feature density, and in turn decreasing the pitch and ultimately making the feature narrower. As the pillar is a truly three-dimensional structure, if there is no scaling of its height, this leads to a mechanical integrity problem. To prevent this from arising, engineers must scale for height, meaning that maintaining an incredibly tight variation feature-to-feature actually produces an exponentially greater percent difference, known as coplanarity. Uniformity cannot stay the same or even incrementally improve. It must improve greatly, feature to feature. The unwanted consequences are genuine challenges in realising the coplanarity necessary to yield.