CS Mantech: Improving the performance and production of the InP transistor

Leading producers of InP HEMTs and HBTs have increased the gain, efficiency and yield of their devices through process improvements and refined epitaxial structures.

BY RICHARD STEVENSON, EDITOR, CS MAGAZINE

With interest in AI at fever pitch, it’s easy to understand why the supporting technologies are generating eye-catching headlines. There’s positive press surrounding the manufacturers of InP lasers, used to transfer data, and the supporting cast, including the producers of InP substrates. Makers of these devices and their foundations are now darlings of the stock market, given their phenomenal gains in share price over the last year or so.

Table 1. The InP technology nodes at Northrop Grumman.

Against this backdrop, the progress of other important classes of InP devices – including HEMTs and HBTs – are attracting less attention. But these gains are valuable, given that the InP transistor is the trailblazer when it comes to delivering high-quality amplification at incredibly high frequencies. Thanks to this, InP transistors are deployed in radar, atmospheric sensing, communication systems, and high-speed test and measurement equipment.

The manufacturers of these devices are continuing to make progress on a number of fronts, including performance, yield and reproducibility. These advances featured at this year’s CS Mantech, held in mid-May in Portland, Oregon, with papers on this theme presented by Northrop Grumman, Teledyne Scientific and WIN Semiconductors.

Figure 1. For Northrop Grumman’s IACC70 HEMT, the gate recess depth and barrier thickness determine critical characteristics, such as transconductance, threshold voltage and gate leakage.

Serving space applications
Northrop Grumman has developed an InP HEMT technology that’s claimed to be cutting edge, in terms of its high frequency, low noise and low-DC-power electronics. One key feature of this device is its InAs composite channel (IACC) that enables operation up to 1 THz, when employed in conjunction with aggressive device scaling.

Efforts are being directed at improving the capability of this technology through the shrinking of device dimensions and an increase in the indium content of the channel from In_0.6Ga_0.4As to InAs (see table 1). Devices with a 100 nm gate length and a In_0.6Ga_0.4As channel are already serving in a number of applications, while those at more advanced nodes are under development.

There are opportunities for Northrop Grumman’s InP HEMT technology in government and commercial sectors, and in particular in communications with high-bandwidth requirements, as well as in radar and atmospheric sensing. The company’s technology is already demonstrating its reliability and high-level performance in two NASA programmes: the Temporal Experiment for Storms and Tropical Systems mission that have deployed InP HEMT technology on cubesats, and provided detailed observations of the microphysics of hurricanes, typhoons and tropical cyclones during three consecutive hurricane seasons; and the Electrojet Zeeman Imaging Explorer, a heliophysics mission that employed three SmallSats to study auroral electrojets – they are the electrical currents that flow 60 to 90 miles above the poles, linking the aurora to Earth’s magnetosphere.

Figure 2. (a) Maps show a significant value of the gate-source voltage of a wafer, for a first generation of Northrop Grumman’s IACC70 HEMT. There is also a significant spread in values for (b) peak trans-conductance and (c) gate leakage current.

At this year’s CS Mantech, Micheal Eller and co-workers detailed efforts to improve the yield of Northrop Grumman’s 70-nm-gate-length HEMTs, a technology referred to as IACC70.

To produce these transistors, Eller and colleagues produce epistructures with an InAs composite channel (see Figure 1 for details). Wet etching and ion implantation ensures device isolation, prior to the use of electron-beam lithography, which defines openings of around 50 nm in an electron-beam-sensitive resist.

A crucial step in the fabrication process is the wet gate recess etch, undertaken before gate metal deposition. This etch removes the InGaAs cap under the gate, and isotropically etches into the InAlAs barrier to form a semi-circular recess.

Eller and co-workers have found that the gate recess etch is the most critical step in the fabrication of the IACC70 HEMTs. There’s significant non-uniformity and poor reproducibility of the epitaxial structure, caused by a within-wafer etch-rate variation and poorly controlled time etching.

Figure 3. Northrop Grumman modified the epitaxial structure for its IACC70 HEMT, adding an etch-stop layer.

Highlighting this variation is a 100 mm wafer map of the gate-source voltage at peak transconductance (see Figure 2 (a)). This metric tends to be more positive as the gate is positioned closer to the channel. The team has also plotted peak transconductance, which is higher when the barrier is thinner (see Figure 2 (b)). However, go too far and the Schottky gate significantly depletes the channel – and forward biasing fails to restore the channel charge and current, due to an excessive gate tunnelling current. The off-state gate-leakage current has also been plotted (see Figure 2 (c)). It increases gradually as the gate recess becomes deeper, and is said to rise dramatically for stronger enhancement-mode devices.

It has been found that the RF performance of IACC70 HEMTs is also very sensitive to the final gate length and the ratio of the gate length to the barrier thickness – its optimal value is about 10, so it is challenging to optimise RF performance and mitigate short-channel effects. There’s the concern that if there’s no etch-stop process, a wide range of gate-recess depths combine with small variations in gate length to produce a significant spread in aspect ratios.

Looking into this matter, Eller and co-workers have considered two standard MMICs: a Ka-band standard evaluation circuit and a Q-band low-noise amplifier. Based on this study, they found that to maintain good DC and RF performance, it is essential to have precise control of barrier thickness and gate length.

To try and fulfil these objectives, engineers at Northrop Grumman have investigated the incorporation of a thin etch-stop layer, embedded within the InAlAs barrier (see Figure 3). This etch-stop layer has a slower etch rate in the gate recess etch than the adjacent arsenic-containing layer, and enables a uniform gate recess depth across the entire 100 mm wafer.

Another modification to the IACC70 HEMTs is the doping of the back barrier, designed to reduce the impact of parasitic access resistance and deliver an additional boost to drain current and device transconductance.

Figure 4. There are reductions in variations associated with the transfer sweep and transconductance in Northrop Grumman’s IACC70 HEMT, thanks to improvements in the epistructure that now features an etch-stop.

Plots of transfer sweeps and transconductance (see Figure 4) underscore the improved process, which has the additional benefit of allowing engineers to tune the lateral gate recess dimension while enjoying minimal impact on gate recess depth. Eller and co-workers claim that they can now modulate important device parameters, such as gate leakage, device breakdown voltage and gate-drain capacitance, in a controlled and uniform fashion that enables them to find the best device configuration.

The new design has enabled a clear increase in uniformity, as well as improved performance. There is a reduction of more than 70 percent in the spread of gate-source voltage at the peak transconductance, a fall of more than 80 percent in the spread of peak transconductance, and an increase of about 0.4 dB in median maximum available gain. Thanks to these improvements, there is a significant improvement in MMIC yield (see Figure 5).

Figure 5. The refined IACC70 HEMT, featuring an etch-stop, has a much higher RF yield than its predecessor. Missing points indicate wafers that have failed line yield tests. RF yield is computed from DC yielding parts, based on specification limits for gain, input/output return loss, and noise figure.

Combining cells, higher powers
At this year’s CS Mantech a team from Teledyne Scientific showcased power amplifier designs. Based on InP HBTs, these amplifiers, operating between 50 GHz and 270 GHz, are claimed to offer a combination of the highest RF output power, power-added efficiency and operational bandwidth.

The designs are constructed using the company’s 250 nm and 130 nm HBT technologies, which are claimed to have a number of attributes, including: the definition of all the technology features for the 250 nm HBTs by optical lithography; use of an accurate physics-based scalable large-signal model; the inclusion of four metal interconnect layers, and a low-loss interlayer dielectric; a metal interconnect layer that prevents RF energy from entering the InP substrate; and thanks to the substrate playing no role in MMIC performance, the opportunity to use RF screening for automatic wafer probing and the identification of known good die.

Recently, Teledyne improved its 250 nm HBT technology, trimming the base-collector capacitance by introducing a smaller metal contact to the HBT base terminal. This has enabled an increase in cut-off frequency, f_T, from 350 GHz to 380 GHz, and an increase in the maximum oscillation frequency, f_max, from 650 GHz to 700 GHz. In comparison, the 130 nm HBT technology has values for f_T and f_max of 500 GHz and 1 THz, respectively, but a slightly lower collector-emitter breakdown voltage – 3.5 V, compared with 4.5 V for the HBTs at the 250 nm node.

Figure 6. Teledyne’s PA cell topology, employed for 50-200 GHz amplification, addresses the challenges associated with a 250 nm InP HBT common-emitter high-power amplifier design.

Engineers produce power amplifier MMICs from these transistors on 100 mm semi-insulating InP substates, with the designs guided by an established Keysight HBT technology model. To suppress PA parasitics in packaged devices, substrates are thinned from around 635 µm to just 76 µm.

The team from Teledyne say that they have invented a novel PA cell topology to address the challenges associated with a 250 nm InP HBT common-emitter high-power amplifier design (see Figure 6). Features of this topology include the biasing of the collector through a vertical DC bus that runs across the input matching networks – this configuration avoids RF output interconnect crossovers, and allows large currents required in InP HBT amplifiers to be distributed along the vertical DC bus. It is said that by avoiding the flow of DC currents across the output matching network or the on-chip combiner, a matching structure is realised with narrow transmission line traces that have a high impedance.

For PA designs operating above 200 GHz, the team from Teledyne use a cascode topology (see Figure 7). With this design, the base node of the common-base device is at DC and RF ground – a condition that minimises parasitic inductance at this node and broadens PA cell bandwidth.

Featuring four gain stages and an 8-way on-chip combiner, the team’s 90-140 GHz PA, based on 250 nm HBT technology, produces a large-signal gain of 13.3-12.4 dB and an output power of 350-430 mW. Building on this design, the team aims to develop a 120-140 GHz PA that delivers more than 0.5 W and has a power-added efficiency of 15 percent.

Figure 7. Teledyne’s cascode power amplifier cell covers 200-320 GHz.

For amplification spanning 140-220 GHz, Teledyne’s engineers have produced an amplifier that has five stages, but no on-chip combiners. Large signal gain across this band is 13-16 dB, when using an input of 0 dBm. There are plans to develop two-way and four-way on-chip combiners, delivering 50 mW and 100 mW across the entire band. The team has employed its 130 nm HBT in a 220 GHz PA that has two gain stages and no on-chip combining. Using an input of 6.9 mW, output is 59.6 mW, indicating 9.3 dB of gain, which is realised at a power-added efficiency of 28 percent. One of the next goals with this design is to increase that efficiency to over 30 percent.

The performance of Teledyne’s PAs has been benchmarked against other results, claimed to be state-of-the-art (see Figure 8). Zach Griffiths and colleagues stated: Results using InP HBTs show a clear performance advantage compared with other solid-state technologies, due to higher gain and available watts-per-millimetre power density.

Figure 8. Teledyne’s power amplifiers are expanding state-of-the-art capability.

Antimony addition
Another producer of InP HBTs is the foundry WIN Semiconductor. At this year’s CS Mantech, the Taiwanese chipmaker reported results on D-band (130-175 GHz) devices, fabricated on its 150 mm line.

In the paper from WIN, Lai-Hsiang Kuo and co-workers pointed out that the D-band is a critical frequency domain for 6G wireless transmission and broadband amplification in optoelectronic ICs.

It is claimed that the InP/GaAsSb double-HBT is a compelling technology at these millimetre-wave frequencies, due to its combination of high values for f_T and f_max and its robust collector-emitter breakdown voltage. In addition, thanks to a type-II base-collector heterojunction, current-blocking effects are mitigated – that’s not the case for conventional type-I InGaAs double-HBT architectures.

Lai-Hsiang Kuo and co-workers are by no means the first to produce InP/GaAsSb double-HBTs, with reports by other teams highlighting the promise of scaling performance to the terahertz regime. However, that body of work has very little to say regarding yield and large-scale manufacturability, with studies tending to be limited to InP substrates with diameters of 100 mm or less.

Addressing those limitations, WIN has introduced the first 150 mm InP double-HBT platform. Its heterostructure consists of an n-type InGaAs cap, an n-type InP emitter, an emitter stabilisation ledge, a p-type GaAsSb base, and an n-type InP collector – as well as an InGaAs etch-stop layer and an InP subcollector, included to aid process control and reduce collector series resistance.

To minimise extrinsic base-collector capacitance without compromising base resistance, the engineers at WIN employ a triple self-aligned process. This begins by using an emitter metal hard mask to define the self-aligned emitter mesa. The next step is the minimisation of emitter-base spacing, realised through precise control of the emitter mesa undercut and a self-aligned base metal deposition. Thanks to these two steps, emitter and base metals can serve as masks, enabling the formation of a self-aligned base-collector mesa.

WIN’s engineers use a hybrid etching scheme, involving both dry and wet etching, to provide mesa isolation. Ensuring high anisotropy and etch selectivity, this is used to produce HBTs with a 0.3 µm emitter width and an emitter-base spacing of 0.13 µm.

Fabrication is completed with back-end-of-line integration, involving three levels of interconnect metal, and the use of benzocyclobutene for surface planarization and the reduction of parasitic capacitance. WIN’s platform also supports multiple passive components, including 50 W/sq thin-film resistors and metal-insulator-metal capacitors with a density of 600 pF mm^-2 (see Figure 9 for an overview of WIN’s technology).

Using small-signal measurements, Kuo and co-workers have determined values of 350 GHz for f_T and 411 GHz for f_max. The maximum power output is 7.41 dB at 6 dB gain compression, according to large-signal 60 GHz load-pull measurements.

Figure 9. WIN has developed a 150 mm InP double-HBT technology. (a) Fabrication process flow. (b) Tilted-view, scanning electron microscopy micrograph. (c) Cross-sectional view of the device. (d) Benzocyclobutene-based back-end-of-line integration platform.

One of the team’s aims is to establish the optimal trade-off between peak device performance and manufacturability with a high fabrication yield. When considering large-signal power performance, they have found that trimming the emitter width from 0.5 µm to 0.3 µm increases the output power density from 2.95 mW µm^-2 to 3.67 mW µm^-2. There are also increases in power gain and power-added efficiency, rising from 10.04 dB to 12.37 dB, and 31.4 percent to 37.5 percent. All these gains are attributed to a 14.4 percent reduction in base-collector capacitance.

Kuo and colleagues have revealed that early process iterations suffered from emitter and base metal collapse, leading to an unsustainable low fabrication yield – it is just 15.4 percent for devices with a 0.3 µm emitter width. This figure has been improved to 87 percent through systematic optimisation of lithographic lift-off parameters.

Figure 10. Yield repeatability across four pilot runs (eight wafers in total) at WIN Semiconductor.

A study of process stability, using four pilot production runs, shows that all wafers have a yield exceeding 70 percent (see Figure 10). This trial confirms repeatability and process uniformity.

In parallel, WIN’s engineers have been enhancing mechanical stability, by refining wafer-handling methodologies. Initial failure analysis found that most wafer breakage originated from mechanical collisions, causing microscopic nicks at the wafer edges that led to catastrophic fractures during wafer transfer. By optimising the wafer transport path and standardising manual handling procedures, the team slashed the breakage rate for 150 mm InP wafers from 6 out of 11 to 1 out of 30.

The poster session plays a prominent role at CS Mantech, helping promote conversation between delegates.

Kuo and co-workers have found that increases to power density and power-added efficiency start to saturate when the emitter width is reduced below 0.4 µm. Based on this observation, an emitter width of 0.3 µm is viewed as optimal, balancing peak RF performance manufacturability and process yield.

The efforts by WIN, as well as Teledyne and Northrop Grumman, highlight the increasing capabilities of InP transistors, in terms of both their performance and the maturity of the manufacturing process. Expect further progress to be reported at next year’s CS Mantech.