World's best gather at Electron Devices Meeting

While studying RF characteristics as a function of temperature, the SFU group recorded what it believes to be the highest ft for a bipolar transistor prior to the meeting; 320 GHz measured at -40 °C (305 GHz at room temperature). The peak in ft comes as the base-collector electric field collapses due to the travelling electron space charge. This collapse occurs at lower currents, and ft roll-off is less sharp as the temperature increases. The base/ emitter capacitance (Cbe) is directly related to transistor operation. The InP/GaAsSb/InP DHBT showed very different behavior to that of a type-I AlInAs/GaInAs DHBT where Cbe rapidly increased at higher currents due to the blocking effect of the potential barrier (figure1). Cbe decreased in the type-II DHBT as current density increased, reaching a minimum as ft peaked. At this point current density was 3 mA/µm2. Above this figure, ft begins to fall as Cbe rises due to increasing carrier storage in the base. Cbe remains low below 3 mA/µm2 because the absence of the alloy blocking effect means no excessive charge is stored in the base.

The announcements of record ft figures continued as Ida et al. from NTT reported an InP/InGaAs DHBT with an ft of 341 GHz at room temperature and a current density of 800 kA/cm2. The NTT group believes its ft to be the highest reported for a bipolar transistor. The high current density was achieved by decreasing the layer thicknesses, although this caused some problems by reducing the breakdown voltage and increasing the collector capacitance. The NTT group used a collector layer that was 150 nm thick to boost current density and to keep a useful breakdown voltage. The collector was compositionally graded and contained a 20 nm InGaAsP layer to suppress the collector current blocking effect. The sub-collector and emitter InP layers were designed with thicknesses to minimize the series resistance.

When the current density was 850 kA/cm2, breakdown voltage was over 2 V, a figure adequate for ECL circuits. The peak ft of 341 GHz was achieved at a current density of 833 kA/cm2. Figures for ft exceeding 300 GHz were achievable with current densities of around 500-1000 kA/cm2.

So, who is right in claiming the ft crown? While the NTT figure for ft is clearly higher, this is achieved at the expense of other parameters of operation. Various figures of merit can be used to analyze the results. Taking breakdown voltage into account by multiplying it by the ft figure puts SFU ahead. Fujihara et al. from NEC showed data using an alternative figure of merit, the product of ft and fmax divided by the sum of ft and fmax. Applying data presented at the meeting to this formula puts the NTT devices at about 130 GHz with the SFU devices at about 160 GHz thanks to a high fmax. "In any case, the NTT 341 GHz result is quite exciting. Very nice work," said SFU s Colombo Bolognesi. New structures for nitrides Low gate leakage current and high break-down voltage are required for high output power AlGaN/GaN HFETs. The integrity of the gate oxide is an important factor in achieving this. Inoue et al. from Matsushita, have proposed an alternative to the deposited oxide, reporting that thermal oxides provide better device performance figures. They fabricated devices with drain currents up to 700 mA/mm, drain breakdown voltages of 130 V and gate leakage currents of less than 1 µA at a drain voltage of 100 V. The AlGaN/GaN HFET structures were grown by MOVPE onto SiC. Device isolation was done by selective area oxidation of the epilayer at 900 °C in an O2 ambient. The gate oxide was formed after the contact regions had been protected from oxidation by silicon. The exposed areas were oxidized at 900 °C in an O2 ambient for 27 minutes. The silicon was then removed and ohmic contacts and electrodes were deposited in the unoxidized areas. Though the quality of the gate oxide resulted in enhanced device performance compared with deposited oxides, the thermal oxide formation time adds significantly to the processing time. The device isolation step took 4 hours for devices with undoped GaN channel layers and 12 hours for those with doped channels.

High power densities in AlGaN/GaN HEMTs require high sheet charge density and electron mobilities. Increasing the aluminum content gives a larger charge density, but reduces mobility because of alloy scatter-ing and imperfections in the crystal lattice. Shen et al. from the University of California, Santa Barbara (UCSB), used an AlGaN/GaN structure that incorporates a 1 nm AlN layer between the GaN and AlGaN. Electron penetration into the AlGaN channel layer from the GaN is reduced due to the different conduction band energies between the GaN and the AlN, and because the binary AlN at the interface does not cause alloy scattering. This decrease in alloy disorder scattering improves mobility, and the larger difference in conduction band energies increases two dimensional electron gas density. Devices fabricated from this structure gave peak currents of 1 A/mm at a Vgs of 2 V and an output power density of 8.4 W/mm with a PAE of 28% at 8 GHz.

The best GaN power FET technologies have been based on the use of SiC substrates. Though sapphire is cheaper and easily available in large diameters, its poor thermal conductance compared with SiC has meant that devices on sapphire have yielded much lower power performance figures. Ando et al. of NEC reported GaN devices on thinned sapphire substrates with performances comparable to those on SiC substrates. The AlGaN/GaN heterostructure was grown by MOCVD on 300 µm thick sapphire substrates. The HFET devices were fabricated and the sapphire substrate thinned by mechanical polishing to 50 µm to aid thermal management. Power measurements at L-band frequencies were performed with the devices packaged in ceramic carriers. An 8 mm wide device gave 11.9 W CW output power, 13.3 dB linear gain and 49.7% PAE at 26 V drain bias. At 16 mm and 32 mm the devices output power increased to 22.6 and 113 W, respectively, while gain dropped to 9.4 and 6.8 dB.

Wu et al. from Cree presented the findings of a study into the bias dependent performance of AlGaN/GaN HEMTs grown on SiC substrates. The devices had gates 300 µm wide and 0.6 µm long, and achieved a power density of 10.3 W/mm, the highest for any FET of the same dimensions. A promising aspect of the devices was their ability to generate a flat PAE plateau of 56-62% at 8 GHz across a wide bias voltage span (10-40 V), ensuring the devices suitability for use across a range of power-supply requirements. The role of surface states Control of surface traps in AlGaN/GaN devices has been recognized as a critical issue for improving device performance (see Compound Semiconductor August 2001, p58). The use of a SiN passivation layer has been shown to markedly reduce surface trapping and hence current collapse in the channel at large bias voltages. Kikkawa et al. from Fujitsu and UCSB demonstrated the combination of a thin n-type GaN cap layer combined with SiN passivation and a recessed ohmic structure (figure 2). The GaN cap layer controlled the polarization-induced surface charge, while the SiN layer stabilized the GaN surface between the source and drain electrodes. Recessing and isolation prevents leakage currents propagating through the surface region to the source and drain electrodes, resulting in an increase of the on-state breakdown voltage from 50 to 70 V.