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Technical Insight

Component makers move towards automated processes

Optoelectronic component manufacturers are currently experiencing considerable downward cost pressure. Bruce Hueners of Palomar Technologies looks at how the component makers are moving towards improved high-accuracy, high-yield automated methods of testing, assembly and packaging.
Even with moderated growth projections, the downward pressure on optical component costs is forcing significant improvements in the processing, packaging and testing of these devices. For key active components such as source and pump lasers, an understanding of the factors that influence yield, performance and reliability are essential to provide lower cost packaging and test solutions. Fabrication and packaging Today, fiber-optic component manufacturing is predominantly a manual process of handling and assembly. These methods include custom wafer processing, thin-film processing, device and subassembly packaging (including eutectic and epoxy component attach and wire bonding), fiber handling and alignment, and the finish steps of tuning, adjusting and testing. Multiple fabrication techniques and processes are common, coupled with a lack of package and material handling standards. A generic process in fiber-optic device assembly is shown in figure 1, and explained below.

Chip fabrication A substrate crystal orientation of (001) is essential for fabricating lasers since parallel mirrors should be made by cleaving the wafer in the (110) plane that is normal to the (001) crystal plane. Grooves 50 µm deep are fabricated by photolithography, with spacing of about 200-300 µm in the wafer to provide scoring lines for chip singulation. Wafers are normally polished from the back-side down to about 100 µm.

Facet cleaving Next, the wafer is cleaved along the direction normal to the grooves in the wafer. At this point in the procedure, special care must be taken to prevent surface damage of the laser, which can introduce dislocation defects that propagate inwards from the chip edges. At this stage, each diode is tested under pulsed operation, and good devices are selected.

Facet coating After cleaving the wafer into diode arrays or bars, both mirror facets are protected by a dielectric film such as SiO2, Al2O3 or Si3N4, which is usually deposited by RF sputtering or CVD. There are two reasons for protecting the mirror surface from exposure to the atmosphere; to suppress oxidation of the facet, which causes long-term degradation, and to reduce surface recombination velocity. This latter parameter is important for catastrophic failure, since a higher surface recombination velocity lowers the critical degradation level.

Die separation The diode arrays are divided into chips by applying stress along the grooves. Only good diodes are selected.

Mount on subassembly This operation includes both die bonding and wire bonding of singulated diodes (see table "Processes for optoelectronic assembly"). Special care must be taken not to introduce thermal or mechanical stress during this procedure. During the device fabrication process, external stress may be applied to the diodes. When cleaving processed wafers into diode arrays, mechanical damage can be induced from the cleaved edge of the crystal. In some cases, dislocations are generated from such regions. During die attach or wire bonding, thermal or mechanical stress is applied to the diode chips, which may accumulate elastic strain in the diode or generate mechanical damage or scratches in the crystal. To minimize stress, this assembly process should be automated and recipe-driven for extremely repeatable and consistent results (figure 2).

Critical considerations Several critical process considerations affect performance and reliability, such as the introduction of stress or mechanical damage during the fabrication and assembly process, and the onset of catastrophic optical damage.

Stress and strain Elastic strain can result from the difference in the thermal expansion coefficient between the epitaxial layers and the electrodes, and insulating films in the chip fabrication process. External stress can also be induced during cleaving of the wafer into diode arrays or during cleaving of the diode arrays in chips. External stress can also be induced during the die-bonding and wire-bonding processes. This stress can be managed with an automated, recipe-driven process.

Mechanical damage Scratches and cracks often arise during the handling of the chips and/or cleaving of the diode arrays. Since mechanical damage and cracks involve a high density of dislocations, they can be origins for rapid degradations and thus should be eliminated. For this reason, manual handling should be minimized and replaced with consistent and predictable mechanized handling. For example, AlGaAs/GaAs high-power lasers degrade rapidly through the generation of DLDs (dark line defects). DLDs propagate from cracks or from regions of mechanical damage that exist in the active layer far away from the active region where weaker light emission is generated.

Catastrophic optical damage (COD) This defect is normally detected at the subassembly level when the laser chip is tested under power. In extreme cases, facets in degraded diodes are scorched during the lasing because critical optical power density has been exceeded. Failure mechanisms include DLDs and dislocations. The mechanism of catastrophic failure typically proceeds as follows:

• During pulsed lasing operation, rapid non-radiative recombination occurs at the mirror surface, causing a decrease in the bandgap of the active layer.

• Strong optical absorption occurs at the mirror, causing a local temperature rise and a further decrease in the bandgap.

• Above certain COD power levels, this positive feedback gives rise to thermal runaway up to the melting point.

• After the pulse, the molten region at the facet cools rapidly and is recrystallized, and a large number of dislocation loops and microdefects are quenched into this region to compensate for the volume change from liquid to the solid phase. The highly defective region terminates in the form of dark areas, which are likely to be non-crystalline, amorphous regions.

• When the next current pulse is applied, the same phenomenon occurs and the molten region propagates from the mirror surface to deep into the inner crystal region of the active layer until the optical power drops below the critical value (Ueda). Higher reliability, lower costs The packaging process for an optoelectronic device challenges efforts to reduce costs. Because the purpose of an optical component is to manipulate light, the design rules for packaging are significantly more complex than those found in the semiconductor industry. With semiconductors, advances in wafer processing drive technology, and packaging is very automated and planar. With optical components, the front-end process is significant, as we have seen, but equally important for photonic devices are package design, controlled assembly processes and meeting critical assembly tolerances.

The importance of recipe-driven process control for optoelectronic assembly can be illustrated by considering the case of attachment of a laser diode within a source or pump laser. This is an extremely temperature-sensitive device that requires careful process control during assembly. Laser operating temperature is a key factor in device reliability as threshold current tends to rise with temperature, increasing the amount of waste heat generated. Furthermore, laser lifetime decreases as temperature increases. Given these device requirements, it is clear that recipe-driven process control is essential in the fabrication of laser diodes.

Laser diodes are attached via a low-ohmic, high-thermal conductivity metalization in a precisely controlled place and eutectic reflow process (figure 3). The reflow profile during an automated in situ eutectic die attach process is engineered to provide consistent melting and a void-free attach interface. This results in smooth heat transfer from the diode and contributes significantly to temperature stabilization during laser operation (figure 4).

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