Indium phosphide ICs in strong demand for 40 Gbit/s networks

Companies such as TRW and HRL have a long history of developing InP ICs for military and space applications. Now these companies (TRW through its Velocium subsidiary) are addressing commercial markets. They have been joined by firms such as Vitesse and Alpha in the US, NTT Electronics (NEL) and Hitachi in Japan, and by foundries such as Global Communication Semiconductors (GCS).

The key factor is performance. In a paper at this year s GaAs Mantech conference, Mike Sun of Alpha Industries Sunnyvale Operations summarized the performance advantages of InP HBTs. "The most attractive features of InP DHBTs are low power consumption due to their low turn-on voltage, and a high Johnson limit due to the high breakdown of the InP collector," he says. "Also they allow moderate circuit integration levels up to a few thousand transistors, and offer the potential to integrate optoelectronic devices such as photodetectors."

So why is this happening now? A key factor is the growing demand for high-speed devices, which has led IC manufacturers to invest in the commercialization of their technology. The article by Velocium in this issue (see "The path to InP production") describes some of the crucial steps in transferring technology from the lab to the fab. In many cases it has proved possible to leverage the process steps and equipment used in GaAs IC manufacturing, but the availability of materials has been a different matter. A key factor in the birth of the InP IC industry has been the recent availability of 4 inch InP wafers with suitable properties (see "Substrate makers tackle the growing challenges of InP"). For companies lacking internal epitaxy capabilities, the availability of 4 inch InP epiwafers has also allowed them to establish their own processes.

Velocium

In May 2001 TRW formed a commercial subsidiary, Velocium, to manufacture and sell high-speed GaAs- and InP-based ICs for fiber-optic and wireless communication systems. The company built the world s first 4 inch InP line, and has now introduced a range of InP-based ICs, including a 40 Gbit/s photoreceiver, a 12.7 Gbit/s NRZ-to-RZ converter and a divide-by-2 frequency divider targeted at down-conversion or phase-locked loop applications. The latter product (DV2401) is rated at 27-43 GHz, although performance extends up to 50 GHz. Features include a dynamic divider design, a single -4 V power supply, on-chip termination (50 Ω to ground), single-ended input and differential output, and a die size of 1.1 x 2.0 mm2.

HRL Laboratories

One indication of the level of interest in InP technology at the recent Optical Fiber Communication (OFC) conference was the appearance of HRL Laboratories of Malibu, CA. HRL s commercial activity in the fiber-optic market is complementary to the work being carried out on behalf of its owners - Boeing, General Motors and Raytheon - in the automotive, defense, commercial airframe and space businesses. According to Marko Sokolich, research department manager of IC Process Engineering at HRL, the cumulative demand for ultra-high-performance circuits in these five broad business areas is modest but important, and all the areas benefit from InP. "By serving these markets with our flexible, high-performance InP processes we are able to enhance yield, reproducibility and reliability in an efficient manner," he says. "In this way we are able to reduce all of our customers costs to access this technology."

Sokolich says that HRL exhibited at OFC in order to showcase its InP foundry and design service capability. "We were particularly interested in educating the fiber-optics market about HRL s history of InP development, dating back to 1988," he says. "Our InP technologies have demonstrated a number of benchmark high-performance millimeter-wave and mixed-signal circuits over the past decade."

Recently, however, HRL has been engaged in the design and demonstration of high-speed digital circuits for 40 Gbit/s and higher fiber-optic communication applications. "Circuits built in our technology have gone into several OC-768 transceiver prototypes for various customers," says Sokolich. "In 2001 we shipped the wafer equivalent of 10,000-20,000 ICs for 40 Gbit/s systems."

HRL offers a "modest volume" fabrication capability in state-of-the-art InP SHBT, DHBT and HEMT processes, as well as design services for fiber-optic communication building-block circuits. The company has developed a first-generation (G1) InP SHBT process with ft and fmax values of 80 and 120 GHz, respectively, and a G2 InP SHBT process with ft and fmax values of >150 and >180 GHz, respectively (see Compound Semiconductor October 2001, p51). During 2002, HRL plans to release a G2+ InP SHBT process with ft and fmax values of >190 and 250 GHz, respectively, as well as a G2+ InP DHBT process with ft and fmax values of 150 and 300 GHz, respectively, and a breakdown voltage (BVceo) of >9 V.

However, Sokolich believes that process parameters do not tell the whole story. "We believe that discrete transistor metrics are necessary but not sufficient for an IC technology," he says. "We have also demonstrated a number of important circuit-based metrics." For example, HRL has fabricated a static divide-by-2 IC operating at >65 GHz, and demonstrated a 60 GHz packaged version in its booth at OFC. Divide-by-4 ICs operating at >65 GHz and divide-by-8 ICs operating at >70 GHz have also been fabricated.

Other ICs include: a 2:1 mux and a 1:2 demux, both operating at >50 Gbit/s; a 40 Gbit/s modulator driver with Vdiff = 8 Vpp and Vse = 4 Vp; and 4:1 mux and 1:4 demux ICs operating at 40 Gbit/s.

Vitesse converts 4 inch fab to InP

Vitesse was one of the first manufacturers to announce its intention to use InP ICs for 40 Gbit/s applications (see Compound Semiconductor April 2000, p7). Vitesse s fab in Camarillo, CA, which originally manufactured GaAs MESFET products, has been converted to a 4 inch InP wafer fab. The company has developed a series of products and is also offering foundry services using its first-generation (VIP1) single-HBT process. According to Alan Huelsman, director of Vitesse s InP program, the process uses a mesa-isolated npn structure that leaves room for further advances through device scaling. "Implementation of this transistor design allowed us to bring up a manufacturable process with adequate performance in a very short period of time," he says. "Fab yield has been excellent and typically runs at about 85%. Circuits with less than 100 transistors often show 100% yield, and the largest circuit built to date in this process - a 4:1 mux containing 2500 transistors - shows very good yield."

The MBE-grown epilayer structure used by Vitesse includes an InP emitter and a Be-doped base, and aluminum interconnect technology was adopted from Vitesse s GaAs process. The transistor performance peaks at a collector current density of about 1 mA/µm2, and the ft and fmax values at this density are both >150 GHz. The BVceo is 4.2 V for the SHBT process, and a DHBT process with a BVceo of >7 V, targeted at lithium niobate modulator drivers, is under development.

"The VIP1 process was frozen in August 2001 to allow us to work with foundry customers," says Huelsman. "However, we have a process development team of about 12 engineers who are working on a second version of the process. By moving to smaller dimensions and making other improvements we expect to reach ft and fmax values exceeding 200 GHz."

Huelsman says that Vitesse has built all the key building blocks for the OC-768 physical layer, including a transimpedance amplifier (TIA), a limiting amplifier, a 4:1 mux/ demux pair and a driver with 3.5 Vpp voltage swing. The analog parts are all being sampled to customers.