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Technical Insight

LDMOS turns up the power

LDMOS transistors with a power density of more than 2 W/mm at 1 GHz and 70 V will compete very effectively with more expensive GaN-on-SiC devices for base-station power amplifiers.
GaN HEMTs are ideally suited for high-power, high-voltage RF applications such as base-station amplifiers for mobile-phone systems. The large output powers required in base-station amplifiers necessitate supply voltages of 26-28 V, and in the near future these voltages will migrate up to 48 V. There is no disputing the fact that GaN HEMTs exhibit outstanding RF power characteristics, with reported power densities of 9.8 W/mm at 8 GHz operation with 45% power-added efficiency (Wu et al.). However, these values are for devices grown on expensive SiC substrates.

It is necessary to consider the trade-off between performance and cost. If a GaN-on-SiC device can deliver 10 W/mm, and a Si device generating only 1 W/mm can deliver the same total power with a 10 times larger gate periphery, then the GaN-on-SiC solution will only become attractive if it can be manufactured more cheaply than the larger Si device. A secondary concern is the actual die size, which would become more important in portable devices.

Dual-layer RESURF structure

High breakdown voltages are a direct artifact of the large bandgaps (3.0-6.0 eV) inherent in the AlGaN material system. Silicon, with a bandgap of only 1.1 eV, must work a bit harder in order to achieve the level of breakdown required for devices operating up into the 50 V region. One way to do this is to use a lateral structure, such as the laterally diffused MOS (LDMOS) device shown in the figure, which was devised by researchers at Uppsala University and Chalmers University in Sweden (Olsson et al.).

The high operating voltages required for power-amplifier applications are achieved through optimized design of the drift region between the gate and the drain of the LDMOS transistor. To achieve high breakdown characteristics, the typical LDMOS design relies on a drift region formed by an n-type diffusion well placed in a p-type substrate. Additional control of the behavior of the drift region is obtained by the placement of a buried p-layer (labeled p-top) and a surface n-layer (labeled n-top) at the surface of the drift region, which can be used to generate a reduced surface field (RESURF) structure. The actual channel region of the LDMOS transistor is formed by the lateral diffusion of the p-type base beneath the n+ source contact. So while the n+ poly-silicon gate in this process is 1.5 µm in length, the active MOS channel length created by the p-type diffused region under the poly-Si gate is only 0.3 µm.

Closer examination shows that a depletion region extends into the drift region from both the substrate (formed by the n- drift/p-substrate junction), and from the surface (formed by the p-top/n- drift junction). Depleting from both sides allows an increase in the n-well doping level (which improves the turn-on characteristics and the on-resistance of the device), without decreasing breakdown voltage or causing punch-through in the narrow p-base region.

LDMOS power results

The LDMOS structures were fabricated using a very basic 1.0 µm CMOS process that required only two layers of metal. The implementation of the RESURF region resulted in optimized output characteristics, with an output resistance of 10 kΩmm at a gate-source voltage (VGS) of 3 V. The breakdown voltage of the devices was around 100 V, making them well suited for applications requiring supply voltages up to 48 V. The output power density was greater than 2 W/mm at 1.0 GHz operation and a drain-source voltage (VDS) of 70 V, with a gain of 23 dB at a VDS of 50 V. At 3.2 GHz operation, the power density was more than 1.0 W/mm at a VDS of 50 V, and 0.6 W/mm at a VDS of 28 V.

These data represent the best reported performance to date for Si power MOSFETs. It will be exceedingly difficult for more expensive GaN-on-SiC devices (or SiC MESFETs) to compete with such performance, when one considers that the LDMOS devices are fabricated in a very basic CMOS process requiring absolutely no specialized processing techniques.

Further reading

Y-F Wu et al. 2001 IEEE Trans. Elec. Dev. 48(3) 586.
J Olsson et al. 2002 IEEE Elec. Dev. Lett. 23(4) 206.

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