News Article

Removing The GaAs Via Hole Etch Process Bottleneck

Increasing the speed of GaAs backside via etching is the current mission for manufacturers of dry etch tools. Young Cho and Jim Thomas of equipment manufacturer Tegal explore the new problems that high etching speeds bring, and suggest strategies for how they can be solved.
GaAs backside via etching is one of the most critical processes in the manufacture of GaAs MMICS. Contacts through via holes provide low inductance grounds that are critical to the performance of FETs and MMICs (Williams). Since the process was initially developed, much effort has been invested in increasing the etch rate and therefore reducing both the process time and the manufacturing costs.

GaAs backside via etching has a reputation as a bottleneck process in MMIC manufacturing. The drive to eliminate this bottleneck has stimulated great competition between dry-etch equipment manufacturers to increase the etch rates of their tools.

However, the strong demand for a high-rate backside via etch has not yet been fully satisfied in the GaAs device industry. GaAs provides a number of performance advan-tages for high-speed devices, but the complicated material properties of compound semiconductors require comprehensive work on process development.

At Tegal we have carried out a project to develop a high-rate GaAs via etch, exploring how process parameters such as chamber pressure and wafer temperature affect the etch rate and the factors that need to be considered in order to ensure defect-free vias.

A new process window

The etching experiments described below were carried out on 4 inch GaAs wafers using Tegal s HRe (high-density reflected electron) plasma-etch tool. The plasma-etch process involves introducing a gas containing an element, in this case chlorine, that is reactive with the material to be etched. A plasma is struck in the Cl gas mixture, forming charged Cl radicals that are accelerated towards the substrate by the application of a DC bias. These radicals react with the GaAs, forming volatile gaseous AsCl3 and GaCl3 species which are pumped away. Using a DC bias means that the etchant radicals are accelerated vertically down onto the substrate, so features with high aspect ratios such as via holes can be etched.

Maintaining the plasma density and uniformity at high pressure is very important for achieving a high etch rate. A high pressure means that there is an abundance of the reactive species available. Energetic free electrons within the plasma impact with the heavier Cl-containing molecules, breaking the chemical bonds and thereby releasing charged Cl radicals for etching.

It is well known that conventional reactive ion etch and inductively coupled plasma tools have difficulty sustaining a high-density plasma at chamber pressures over 20 mTorr, because the mean free path of electrons reduces as the pressure rises. In the HRe, permanent magnets at the top of the chamber and at its sidewalls reflect free electrons back into the plasma, making it possible to maintain a high plasma density at high chamber pressure. This provides a new window of process parameters to explore.

For the development of a high etch rate process in the HRe, a 13.56 MHz generator was used for plasma generation, and 450 kHz was chosen as the bias power frequency. The GaAs wafers were coated with an AZ4620 photoresist etch mask and patterned with 50 µm diameter holes more than 100 µm apart. RS/1 data management and analysis software from BBN Corporation was used for designing the experiment and analyzing the results.

Performance under pressure

Figure 1 shows the GaAs etch rate as a function of the source power and chamber pressure. The results show that pressure has a much stronger influence on GaAs etch rate than the source power. The etch rate also shows a linear increase with increasing pressure. This implies that the GaAs etch rate is limited by the amount of chlorine radicals present. Therefore the key to achieving a high etch rate is to provide sufficient reactant at a high chamber pressure. The highest etch rate achieved was more than 10 µm/min at a chamber pressure of 35 mTorr.

Figure 2 shows the etch selectivity to photoresist for the same process parameters as figure 1. A maximum selectivity of 27:1 was achieved at the highest chamber pressure. The etch rate of the photoresist is dominated by the DC bias and the energy of the etchant ions. The etch rate for GaAs is largely chemically dependent so it increases at higher pressures. The photoresist etch rate therefore remains more stable than that of GaAs as the pressure rises, improving the etch selectivity.

CS International to return to Brussels – bigger and better than ever!


The leading global compound semiconductor conference and exhibition will once again bring together key players from across the value chain for two-days of strategic technical sessions, dynamic talks and unrivalled networking opportunities.


Join us face-to-face between 28th – 29th June 2022

  • View the agenda.
  • 3 for the price of 1. Register your place and gain complementary access to TWO FURTHER industry leading conferences: PIC International and SSI International.
  • Email info@csinternational.net  or call +44 (0)24 7671 8970 for more details.

*90% of exhibition space has gone - book your booth before it’s too late!

Register


×
Search the news archive

To close this popup you can press escape or click the close icon.
×
Logo
×
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
Live Event