News Article

Old Dogs And New Tricks

The ubiquitous gate oxide material from the silicon industry, SiO2, has been successfully used to demonstrate GaN-based MOSFETs that rely on the properties of the GaN-SiO2 interface.
The remarkable chemical and physical nature of the SiO2-Si interface has been critical to the growth of the IC industry. Not only can SiO2 withstand incredible breakdown fields in the order of 1 x 107 V/cm (resulting in breakdown voltages of 10-20 V for an SiO2 thickness of only 10 nm), but it also has a mid-gap interface-state density of only 2 x 1010/cm2eV. These characteristics have made it the perfect interface at which to store, inject and manipulate charge, making all CMOS operations possible.

Unfortunately, such a high-breakdown, low-interface-density oxide does not exist for III-V compounds. III-V devices are therefore not fabricated around an insulator-semiconductor interface, but employ metal-semiconductor interfaces, or interfaces between semiconductors of varying bandgaps. A quality oxide-III-V interface would only further improve the impressive capabilities and applications of III-V devices.

The usual suspect

Does such an oxide exist? Perhaps. Researchers are beginning to wonder if the ideal candidate might be that old favorite - SiO2. In a rather ironic fashion, the III-V material system that is giving this veteran oxide a look is the very newest device-material system - GaN.

Despite the rapid improvement in GaN devices, almost all of which rely upon the AlGaN-GaN hetero-interface to modulate and control charge, an ongoing limitation, and challenge to further device improvements, is GaN surface passivation. This issue must be resolved to improve surface breakdown voltages further and to reduce leakage currents (critical parameters for both high-power and RF applications).

When fabricating GaN Schottky diode photodetectors, Asif Khan and coworkers found that record-low leakage currents could be obtained by using SiO2 to passivate the GaN surface. This led to the incorporation of SiO2 beneath the gate of a conventional AlGaN-GaN HFET (Khan et al.). Using a 13 nm PECVD-deposited SiO2 layer between the otherwise standard gate and AlGaN layer, the resulting device exhibited gate-leakage currents that were six orders of magnitude lower than those of the control HFET (identical to the MOS-HFET except for the insertion of the 13 nm SiO2 layer). This also allowed for a larger gate voltage swing and higher linearity, which should enable a device with less intermodulation distortion, less phase noise and a larger dynamic range. While these improvements are certainly desirable, the actual MOS-HFET is still essentially an HFET where current transport takes place at the AlGaN-GaN interface, and the SiO2 layer is used to passivate the surface of the AlGaN.

With these initial successes, researchers are beginning to explore the possibility of a true GaN MOSFET, where the SiO2-GaN interface is integral to the charge transport through the device (see figure). Fabricated by a research group from the National Cheng Kung University in Taiwan, this device relies on the quality of the SiO2-GaN interface. Furthermore, a novel liquid-phase deposition (LPD) process is used to deposit the SiO2,, rather than relying on a PECVD SiO2 layer as typically used by III-V workers (Lee et al.).

Liquid-phase deposition

LPD requires little more than a temperature controller, a pH meter, a substrate holder and a Teflon container. A supersaturated hydrofluosilicic acid aqueous solution (H2SiF6 - 0.4 molar) acts as the Si-source liquid and a boric acid aqueous solution (H3BO3 - 0.01 molar) is used to control the deposition rate. These solutions are used to deposit SiO2 at 40 °C and an approximate rate of 50 nm/h.

The highest-quality oxides are achieved for the lowest growth rates. For the device illustrated in the figure, MOCVD was used to first grow a 1.0 µm undoped buffer, followed by a 200 nm Si-doped (5 x 1017/cm3) channel layer, and lastly a 20 nm heavily Si-doped (2 x 1018/cm3) contact layer. Device isolation and GaN etching to define the contact regions were performed by photo-enhanced chemical etching using KOH with a pH of 13.5, under a light intensity of 25 mW/cm2, resulting in an etching rate of 50 nm/min. Ti/Al/Au was used for contact metallization, followed by LPD of SiO2 that proceeds selectively only on the exposed GaN. This not only coats the channel area, but also passivates the exposed GaN-mesa sidewall.

Excellent performance

The SiO2 used in this device was 85 nm thick, exhibiting an RMS surface roughness of 5.2 nm, a breakdown field in excess of 5 MV/cm and an interface-state density of about 2 x 1011/cm2eV. The leakage current of 1 x 10-7A/cm2 is comparable to that observed in the MOS-HFET. The breakdown field is half of that observed for SiO2 grown on Si, and the interface-state density is approximately an order of magnitude greater - excellent values compared with those obtained in many other efforts to form SiO2-III-V interfaces.

Using a gate that is relatively long (8 µm) and 40 µm wide, the gate bias was ramped from 6 to -8 V. The device exhibited a transconductance (gm) of 48 mS/mm and a drain current density (Ids) of 250 mA/mm at a Vgs of 4 V and a Vds of 20 V. The gm is almost twice that of a GaN MESFET control device of similar structure.

While these devices do not yet measure up to those reported in AlGaN/GaN HEMT structures, this represents the first reported attempt at using the SiO2-GaN interface in such an FET device. The performance can undoubtedly be improved by optimizing the SiO2 quality (especially critical will be the ability to use thinner gate oxides, while maintaining good breakdown characteristics) and reducing device geometries. In addition, the true potential of such structures will only become clear once RF measurements are performed.

Despite these outstanding issues, a first step has been taken, combining the standard oxide that is the workhorse of the semiconductor industry with the newest semiconductor device material.

Further readingM Khan et al. 2000 AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor IEEE Elec. Dev. Lett. 21(2) 63.
K Lee et al. 2002 GaN MOSFET with liquid phase deposited oxide gate Elec. Lett. 38(15) 829.

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