High Performance CMOS Within the compound semiconductor manufacturing community, it is well recognized that technologies such as SiGe HBTs, Si bipolar and even Si BiCMOS can represent stiff competition for both high speed and RF applications. But when it comes to basic CMOS, while most will concede to its intrinsic cost advantages, few consider it a serious threat due to what is believed to be its inherently lower performance. While this sentiment was true a few years ago, it certainly no longer is. Emerging from universities and research labs are a wide range of advanced CMOS circuits that can compete head-to-head with the most advanced compound semiconductor devices. A team of researchers from the University of California San Diego, IBM and the Space and Naval Warfare Systems Center have reported on a bulk silicon divide-by-two dynamic frequency divider operating with a maximum clock speed of 26.5 GHz [1]. While the best III-V devices have pushed such dividers up to 80 GHz, performance in the 20 GHz range should be more than sufficient for the most demanding digital commercial applications. Excepting the fact that smaller than standard CMOS gate-lengths were used (0.1 m), the process itself was quite basic, using a single n-well process, a relatively lossy 1.2 ohm-cm p-type substrate, and only two levels of metallization. Using 3.0 nm gate oxides, and operating at a drain to source bias of 0.8 V and a gate to source bias of 0.8 V, the devices exhibited a breakdown voltage of over 3V and an ft of 95 GHz. In order to achieve the maximum possible speed with the process, an all-NMOS design using source-coupled FET logic (SCFL) was used. The divider operated over a range of 6.5 to 26.5 GHz, and consumed only 26 mW of dc power at a clock frequency of 20 GHz. This represents compound semiconductor-like performance for a relatively basic CMOS process (note that not even an SOI substrate was used). Other recent digital CMOS work targeted specifically at OC-48 SONET receiver applications (2.5 Gb/s) has been reported by researchers at Bell Labs [2]. In a typical SONET receiver, the incoming optical signal is received and converted by a detector (in this case an avalanche photodiode or APD) into a current signal. In turn, a transimpedance amplifier (in this case with a value of 1.5 k) converts this current into a voltage signal. Before this signal can be passed along to the clock and data recovery circuit (CDR), and from there into the DEMUX, it must be amplified. This amplification can be done either by an automatic gain control amplifier (AGC), or a limiting amplifier, which by definition is used to limit amplification to avoid output saturation (and as a result the loss of the incoming signal). Typically, a DFB laser would launch a signal into the fiber at a power level of 2 dBm, which after 100 km of travel would be attenuated to 28 dBm. To adequately amplify this signal a limiting amplifier with a gain of 3032 dB is required. Furthermore, if implemented in CMOS, the limiting amplifier, CDR, DEMUX, MUX and SONET framer could potentially be fabricated in a single CMOS chip. This would then require only an external transimpedance amplifier (which typically is in close proximity to the APD to minimize parasitic capacitance) and the laser/modulator to complete the transceiver. Using a 0.25 m bulk CMOS process, a CMOS limiting amplifier operating at 2.5 V was fabricated that exhibited a bandwidth of 3 GHz and a noise figure of 16 dB, while consuming only 53 mW. Such performance opens the way to an integrated CMOS SONET OC-48 solution, and represents real competition in an application that is often implemented in GaAs MESFET technologies. Driven by the need for wireless LANs operating at high data rates (i.e. 50 Mb/s) in the 5 GHz band (which the FCC has allocated for unlicensed national information infrastructure use), researchers at Bell Labs are also investigating the use of CMOS in the fabrication of a 5 GHz transceiver front-end chipset [3]. Using a 0.25 m bulk CMOS process that features 5 layers of metal, and thick metal inductors with a Q of more than 10, the entire transceiver (full receiver and transmitter, except for a final external power amplifier needed on the transmitter side) is fabricated on two chips. The receiver contains an LNA with a 2.5 dB noise figure and 16 dB power gain and receiver mixer with 12.0 dB noise figure and 13.7 dB gain. The transmitter achieves an output power of 2.5 dBm at 5.7 GHz, with 33.4 side-band rejection by using an integrated quadrature VCO. By comparison, more advanced Si processes using BiCMOS or SiGe typically report less than 10 dBm of transmit power. Operating from a 3 V supply, the power consumption for the receiver and transmitter are only 114 and 120 mW, respectively. These three examples clearly demonstrate the potential of CMOS to compete in a wide range of applications, including those which are often considered the exclusive domain of compound semiconductor devices. References: [1] M. Wetzel et al, IEEE Microwave and Guided Wave Letters, 2000, Vol. 10(10), p. 421. [2] E. Sackinger et al, IEEE Journal of Solid State Circuits, 2000, Vol. 35(12), p. 1884. [3] T. Liu et al, IEEE Journal of Solid-State Circuits, 2000, Vol. 35(12), p. 1927.