Temperatures reached 100 F in Las Vegas during the 2001 GaAs Mantech Conference. Cooler climates were found inside the meeting rooms where, despite the recent chill in macroeconomic conditions, GaAs remained a hot topic. Marie Meyer reports.

The GaAs industry may be in a slump, but there was little evidence of that fact on display at the 2001 GaAs Mantech Conference, which was held on 2124 May in Las Vegas, Nevada. The continuing maturation of the GaAs industry, combined with the allure of the venue, contributed to the record turn-out of some 500 visitors, with 100 companies taking part in the exhibit. Supply chain issues Last year GaAs fabs were bedeviled by the most fundamental of problems: a shortage of GaAs wafers. The crisis was brought about in part by the phenomenal growth in consumption of GaAs devices, and the well publicized gallium shortage (see Compound Semiconductor December 2000, p43). But, as Scott Davis of Sumitomo Electric explained, there were also some interesting, less obvious contributing factors, stemming from the transition to 6 inch GaAs in 1999. According to Davis, the more aggressive wafer suppliers were so eager to win a strategic position with first 6 inch fabs that prices fell to unsustainable levels as low as $400/piece in the second half of 1999. At about the same time, suppliers began to notice that yields on 6 inch wafer production were not as high as hoped. "The combination of low prices and yield problems made short-term prospects for profitable business poor," said Davis. "This led to slower investment in new 6 inch production equipment." As a result, when demand began to rise, the wafer suppliers were unable to meet it. When making this point Davis used the phrase "apparent demand" to distinguish it from actual consumption of wafers. Davis noted that there is a significant amount of "double counting" throughout the industry, with all the major wireless handset vendors planning to increase market share, and each device manufacturer planning to supply the power amplifier for each of those phones. And, of course, "every wafer vendor intends to expand their business at all of the major device fabs". Reality, of course, has turned out to be not so rosy, and Davis said that the shortage of wafers experienced last year has now turned into rising inventories for device manufacturers and cancelled orders in the first half of this year. Mixed outlook for GaAs wafers Davis also noted that supply chain issues are intervening in the LEC vs VGF debate. It is generally held that wafers grown using the VGF technique (or one of its variants) offer superior results for epitaxial structures because of their lower dislocation densities. However, there is still some debate on this issue, and LEC might be seen as still having an edge in terms of its cost and the greater maturity of the technology. But, Davis noted, the long lead times that are required to ramp up LEC production are an additional disadvantage of LEC technology. Most LEC crystal growth uses high-pressure chambers that require extensive safety testing before they can be brought on line, stretching the total lead-time for commissioning a new LEC puller out to nearly a year. In contrast, the lead-time for new vertical growth furnaces is 46 months. Currently the GaAs wafer supply situation is a "good news, bad news" scenario. The good news is that the shortage is over. "Capacity for 4 and 6 inch wafers is expected to be more than adequate to meet market needs in 2001 and beyond," said Davis. This is due in part to the fact that the gallium supply situation is rapidly improving (see Compound Semiconductor April 2001, p4), as well as the fact that several major GaAs wafer producers have embarked on ambitious expansion plans (see ). The bad news is that relief is also coming from a very unwelcome corner GaAs fabs are delaying or canceling wafer orders in light of the slowdown in the wireless business. But, Davis reported, the construction of new facilities by the wafer manufacturers is still going through albeit with a moderation of the rate at which new capital equipment is being installed so that the suppliers will be ready to respond when the market picks up again. Recycling GaAs wafers In a separate presentation, Marty Brophy of TriQuint reported another measure that could make a positive impact on the supply chain: recycling of processed GaAs wafers. TriQuint is working with the Swiss company Picopolish to demonstrate that scrapped GaAs wafers can be stripped and repolished. While this process is common for producing "mechanical" wafers that can be used for equipment testing and other experiments, TriQuint is exploring whether this method can produce prime wafers for use in its production process. Brophy reported that less than 10 m of thickness is lost in the recycling process, and the wafers show low defect levels and no metallic contaminates such as gold or titanium due to strip and/or etch residues. No noticeable effect on parametric test results or device yields has been detected when the recycled wafers are processed for the second time. TriQuint and Picopolish intend to continue this work using much larger quantities of wafers to discover whether there are any subtle effects that haven t been revealed by these early trials. GaAs vs silicon In the plenary session, Y K Chen of Bell Laboratories reviewed the choice-of-technology issues in the high-speed IC area, one of the critical technologies for optical networks. Here, compound semiconductor devices serve as technologies that enable higher data rate networks to be implemented, but eventually silicon narrows the performance gap and moves in on the market. The section beginning on page 48 gives a more detailed explanation. The 2.5 Gbit/s market has already been "siliconized" and the same is now happening in the 10 Gbit/s market. The 40 Gbit/s market, however, provides many exciting opportunities for compound semiconductor technologies, including the first high volume application of InP circuits. Another GaAs vs silicon battle is being waged in the area of power devices for wireless infrastructure markets meaning base stations and related equipment, as opposed to handsets. Here the competition comes from silicon LDMOS (laterally diffused metal oxide semiconductor). Lynelle McKay of Motorola reported that "every base station power amplifier design team in the world is currently debating the "LDMOS or GaAs?" question". Not too long ago, it seemed that the fight was already lost. In the mid-1990s LDMOS was shown to provide superior linearity perfectly suited to the relatively low-frequency, linear-cellular modulation formats in use at that time. However, the deployment of 3G cellular in the next few years may present an opportunity for GaAs to make up lost ground. These networks will have the highest frequency operating system of any mobile scheme to date. Most of the world, led by Europe, has allocated the 2.522.67 GHz band. The US is still contemplating the option of using a lower frequency range, but it is generally believed that the FCC will eventually come down in favor of synchronizing with the rest of the world. If so, GaAs will have a significant advantage because of the higher frequency. The decision is an important one and will be watched very closely, because although LDMOS can operate at up to 2.6 GHz (far higher than previously thought), efficiency is greatly compromised above 2.2 GHz. In the meantime, power GaAs suppliers are trying to reclaim lost market share by reducing prices to achieve parity with LDMOS on a $/W basis. McKay reported that the prices of power GaAs devices have dropped by more than 50% in the last year. MEMS applications Olga Blum Spahn from Sandia National Laboratories discussed the promise of GaAs-based MEMS structures. At present, the potential size of the MEMS market is only poorly understood. Spahn noted that when commercialization possibilities do open up, III-Vs should be considered as a candidate material system. They provide two major advantages over silicon: a very rich process chemistry, with numerous selective etch options; and the ability to integrate with optoelectronic devices. Spahn said, "The general scepticism surrounding the mechanical properties of compound semiconductors is largely unfoundedwhile not as strong as silicon, they are sufficiently robust for most MEMS applications." Also in the MEMS area, S C Shen of the University of Illinois reported results from low-voltage MEMS switches fabricated on GaAs using a five-mask layer process that is compatible with standard GaAs MESFET processing. Low-insertion-loss, high-isolation MEMS switches are considered to be one of the most attractive RF applications of MEMS technology. Achieving low actuation voltages is the key. In this report the minimum operational voltage was 9.5 V compared with typical reports that are in the 3050 V range. Metamorphic devices The next weapon that the III-V industry can wield against silicon is InP technology. But, as Bill Hoke of Raytheon told the audience, a 4 inch InP wafer currently costs more then $1000, compared with $450 for a 6 inch GaAs wafer. Moreover, since 6 inch InP wafers are not available, fabs are not able to employ the newest, most sophisticated processing tools. As the diameter of InP substrates is increased, the fragility of InP may become a bigger issue, particularly for processes requiring backside thinning and via holes. Therefore achieving "InP-like" performance out of structures grown on GaAs wafers using metamorphic buffer layers is an attractive prospect. Hoke reported that microwave measurements on an MHEMT device with a 0.13 m gate and In0.53Ga0.47As channel layer yielded an extrapolated peak fT and fmax of 235 GHz and 210 GHz, respectively. Metamorphic devices may even provide some design flexibility that isn t possible in InP-based devices. Hoke gave as an example an MHEMT that contains 3040% indium in the channel and barrier layers. This composition is attractive for increasing the breakdown voltage of the high-gain, high-frequency, low-noise performance of the InP HEMT. This structure cannot be obtained by pseudomorphic growth on GaAs or InP substrates due to combined strain from the barrier and channel layers. A comparison of power-density results at 35 GHz shows that MHEMT devices exhibit a clear improvement over InP HEMTs. HEMTs are not the only devices that can be produced on metamorphic wafers. Dimitri Lubyshev of IQE reported on the growth of metamorphic HBT structures on GaAs substrates that exhibited DC characteristics comparable to conventional HBTs grown lattice-matched to InP substrates. on page 42 shows Gummel plots for metamorphic HBTs (M-HBTs) and conventional lattice-matched devices (LM-HBTs). Lubyshev reported that there was no indication of p-n junction degradation due to interfacial roughness or diffusion of the Be dopant. Orientation dependence In a very interesting presentation from Oki Electric, Tomoyuki Ohshima discussed the effect of the gate orientation relative to the substrate for pseudomorphic InGaAs/AlGaAs HEMTs. For FET devices it is understood the electrical characteristics of the device are gate-orientation-dependent because of the piezoelectric effect (a well-understood phenomenon wherein the influence of the source and drain regions on the channel grows as gate length is reduced). Oki has also observed a relationship in HEMT devices. shows the dependence of threshold voltage on gate length for HEMTs with three different orientations. Threshold voltage decreases as the gate length is reduced, due to the short channel effect. However, the extent of the effect does seem to be related to substrate orientation. Ohshima observed that this is not due to the piezoelectric effect because the threshold voltage did not change before and after the deposition of the silicon nitride film. Instead, it appears to be related to the dependence of etching rate on crystal orientation. Cross-sectional SEM analysis reveals that the profiles of the recessed walls vary significantly, from nearly vertical in the case of the [0-1-1] device to sharply sloping in the case of the [0-11] oriented device. Oki observed that other characteristics of HEMTs such as cut-off frequency (fT), transconductance and gate-to-drain breakdown voltage were also orientation-dependent. New tools and techniques Several of the Mantech presentations dealt with new tools for processing and inspection. Yaozu Wang reported on a yield-enhancement methodology applied to Anadigics new 6 inch GaAs fab using an August Technology NSX system coupled with a defect correlation program that was developed in house. The NSX is an automated inspection tool that can be used to run full wafer inspection and to monitor defects at the critical process steps for MESFETs, HBTs and HEMTs. It correlates the defects-to-die sort yield and parametric results at probe testing, hence improving the yield by reducing the critical defect density. Wang noted that when inspections are done using manual methods, the quality of the results depends largely upon the ability and experience of the inspection operator, and the data gathered are difficult to correlate with yield results. Paul Miller of TriQuint discussed a dry replacement for conventional wet, solvent-based techniques for metal lift-off process steps. The tool used was a system produced by Eco-Snow that generates a stream of solid CO2 particles. In traditional GaAs device manufacturing, interconnect formation uses evaporated or sputtered metal deposited over patterned resist. The bulk of resist and metal is then removed by a wet solvent lift-off process, followed by a high-pressure DI water or solvent spray to remove residual metal. However, the Eco-Snow system relies primarily on a physical mechanism for the removal of residues, eliminating the possibility of metal residues being left behind. S K Jones from Marconi Caswell discussed importing a familiar technique from the silicon industry: process and device modeling and simulation using TCAD (technology computer-aided design). In its annual roadmap for the silicon semiconductor industry, ITRS reports that the use of TCAD can deliver annual cost reductions of 2035%. Nevertheless, Jones said, "While device modeling is used widely in the III-V industry, process modeling is still rather scarce." He explained that Marconi adapted commercial software tools from the silicon industry for use in developing its new 6 inch GaAs PHEMT process. Device geometry and topography were modeled through sequential deposition and etch stages, with the metal evaporation, (PE)CVD nitride deposition, and wet and dry (plasma) etch steps being the specific processes modeled. No attempt was made to model the lithography, due to the lack of detailed experimental calibration required for accurate models of the resist exposure and development. Jones explained how the process modeling was used to choose between three gate processes on the basis of a cost/benefit analysis, with a combined e-beam and optical lithography process being the winner. Bonding to wafer carriers Finally, a presentation from Austrian processing equipment manufacturer EV Group and the Max Planck Institute of Germany discussed different kinds of wafer bonding for GaAs processing. Reversible wafer bonding, done using either wax or an adhesive heat or UV release film, is used during backside thinning and lithography. The GaAs wafer is coated uniformly with wax and bonded to a carrier substrate such as quartz or Si that improves mechanical strength, while the wax protects the active surface of the device. This is referred to as "reversible" bonding because the device and carrier wafers can be de-bonded once the backside processing is complete. Permanent or direct wafer bonding (DWB) can be used for integration of heterogeneous materials, such as GaAs on Si. In the process developed by the EV Group "spin-on-glass" (SOG) layers are used as the bonding material, as shown in . One of the biggest problems in mating silicon with GaAs is the thermal mismatch the thermal expansion coefficient of GaAs is twice that of Si. Therefore the performance of these wafers during annealing is a topic of concern. The results presented showed good results for temperatures up to 280 C above that, they de-bond or shatter. However, after the GaAs portion of the bonded wafer is thinned to 40 m via grinding and then polished by CMP to a final thickness of 510 m, the bonded pairs could be heated to more than 400 C. At this point the contribution of the back-thinned GaAs wafer to the thermally induced stress on the heterostructure becomes negligible.