Recent efforts to develop semi-insulating silicon substrates and fabricate high-Q inductors have involved the use of porous silicon structures, writes Bob Metzger.

As operating frequency ranges push beyond the 0.92.4 GHz bands, which dominate current applications and markets, one of the greatest challenges facing silicon for higher frequency operation is the lack of a truly semi-insulating substrate. Such substrates are critical to fabricating high-Q inductors a crucial element in almost all monolithically-integrated RF devices. Unlike GaAs or InP substrates, which can be made semi-insulating, silicon has typically been forced to rely upon the insulating properties of SiO2 for isolation. While SiO2 is an excellent DC electrical isolator, effective operation in RF applications requires the SiO2 to be thick, in order to capacitively isolate it from the underlying conducting silicon substrate. The challenge to implementing thick SiO2 layers is two-fold. The first (physics related) challenge results from the difference in the thermal expansion coefficients of silicon and SiO2. Thick oxides are typically grown in the 10501150C range or deposited by a CVD process. Upon cooling the stresses generated as a result of the difference in thermal expansion coefficients can actually shatter a silicon substrate when the oxide exceeds a thickness of 50 m. The second challenge is based on economic and manufacturing considerations. The fabrication costs and the time required to grow (or even deposit by CVD) such thick oxides by any conventional techniques make the implementation of thick oxides unrealistic in a real manufacturing environment. Enter porous silicon A potential solution to both these issues is the use of porous silicon. In this material, the lattice has had a large number of its silicon atoms removed by an electrochemical reaction, producing a honeycomb-like structure that exhibits markedly different structural and electrical characteristics compared to conventional silicon. In particular, porous silicon exhibits a resistivity of the order of 106 .cm, a value approaching the semi-insulating resistivity values achieved in GaAs and InP substrates. Forming porous silicon Porous silicon formation is typically carried out in an electrochemical cell using a 25% HF solution (HF:ethanol with a 1:1 volume ratio), with the silicon substrate acting as the anode and a sheet of platinum as the cathode. Anodization, which takes place at room temperature and at a current density of 50 mA/cm2, can transform single crystal silicon into porous silicon at a rate of approximately 12 m/min. Initial work on using porous silicon for RF applications focused on the oxidation of the porous silicon layer (Nam and Kwon). Because of the honeycomb structure, rapid thermal oxidation can be performed due to enhanced oxygen diffusion through the porous material: in less than one hour, an oxidized porous silicon layer of 30 m can be achieved. Using such a layer, a 6.29 nH inductor was fabricated that exhibited a resonant frequency of 13.8 GHz and maximum Q of 13.3. Such performance characteristics make this a suitable manufacturing process for silicon MMICs operating up to 12 GHz. However, the same thermal expansion coefficient constraints limiting the thickness of thermally grown oxides in single crystal silicon still exist in the case of oxidized porous silicon, limiting the total thickness of the oxidized layer to 50 m. Recent research (Kim et al.) has focused on leveraging the highly insulating nature of porous silicon. In fact, it may not be necessary to oxidize the porous layers for RF applications, but merely rely on the insulating nature of the porous silicon itself. The authors prepared porous silicon layers ranging from 50200 m in thickness using conventional porous silicon formation on a heavily doped silicon substrate (0.007 .cm). A 2 nm oxide layer was subsequently produced at 300C to stabilize and passivate all the internal surfaces of the porous silicon. The use of a highly-doped substrate allows the selective transformation of regions of the silicon substrate into highly resistive layers through the porous silicon process, while other regions of the substrate then become available for conventional silicon CMOS or BJT fabrication. Pushing silicon RF performance Spiral inductors with L values of 5.7 nH have been fabricated using the above method. These exhibited maximum Q values of 29 at 7 GHz, and a resonant frequency of greater than 20 GHz. It was observed that the resonant frequency increased with porous silicon thickness, and saturated when the thickness exceeded 120 m. This was accompanied by a corresponding decrease in total capacitance as the porous silicon thickness increased, with Q increasing monotonically with thickness beyond the 200 m level. Values such as these show that porous silicon structures have the potential to push the RF operating window for silicon MMICs well into the 20 GHz range, offering real competition in a regime that many consider the exclusive domain of GaAs and InP. Further reading C Nam and Y Kwon 1997 IEEE Microwave and Guided Wave Letters 7(8) 236. H Kim et al. 2001 IEEE Electron Device Letters 22(6) 275.