News Article

InP HBT Technology Targets High-speed Communications (Microelectronic Devices)

InP HBT technology offers several advantages over other technologies for 40 Gbit/s circuits, writes Marko Sokolich. The first transatlantic fiber-optic cable TAT-8 was pressed into service in December 1988 with the intention that it should meet the needs of data and voice communications across the Atlantic until the year 2000. Two years later the cable was filled to capacity. Since then data-transmission capacity across the Atlantic has increased by a factor of 1000. About half that increase (a factor of 35) came from the increase in speed of each channel s electronics, which went from transmission rates of 280 Mbit/s in 1988 to 10 Gbit/s today. The remaining boost in bandwidth was obtained by increasing both the number of fibers and the number of channels per fiber (using WDM). This prototypical long-haul line is just one example of the rapid deployment of the fiber-optic infrastructure. During the same period, over which communication capacity was growing by a factor of 1000, the speed of the fastest electronics (as measured by the maximum clock rates of benchmark circuits) increased by only a factor of three (). In 1988 the required bit rate, 280 Mbit/s, was not a difficult target for any of the advanced technologies, including the fastest Si bipolar, GaAs MESFET and advanced CMOS processes. More exotic "laboratory" technologies, such as GaAs HEMT or the newly demonstrated SiGe and InP were certainly not needed. The rapid rate at which bandwidth has been consumed has led a traditionally conservative industry telecommunications to lead the way in some of the most exotic technologies. Currently, advanced processes in SiGe, CMOS, GaAs and InP are being evaluated for various OC192 (10 Gbit/s), OC768 (40 Gbit/s) and Gigabit Ethernet (1, 10, 100 Gbit/s) applications. Data-transmission requirements have now caught up with state-of-the-art electronics. The background of the technology By posting some of the more impressive speed and power benchmark results, material systems lattice-matched to InP have become front-runners in the race to find a technology to support 40 Gbit/s transceivers. Recently, 300 GHz current-gain cut-off frequency (Dvorak et al.), 800 MHz maximum frequency of oscillation (Lee et al.), 330 GHz gain-bandwidth product (Baeyens et al.) and 70+ GHz clock rate (Sokolich et al., Mathew et al.) in a static divider have been reported. Some of these results have been demonstrated in IC processes capable of more than 2000 transistor circuits with logic gates operating at a few milliwatts at a clock rate above 30 GHz. HRL Laboratories LLC has been developing InP circuits since that first transatlantic fiber-optic cable went into service. During the course of that pioneering work we have set many of the standards by which high-speed IC technologies are judged, and have demonstrated a number of circuits with both the speed and complexity required to satisfy the needs of high-data-rate communications. Advantages of InP HBTs InP HBTs have many advantages over other electron device technologies. As has been clear in the Si industry for many years, the fastest logic is made using bipolar devices in differential logic families because of the exponential turn-on, superior transconductance and better turn-on matching of bipolar transistors. Semiconductors lattice-matched to InP have a significantly lower turn-on than GaAs, and they have a higher cut-off frequency and lower power-delay product than either GaAs or SiGe. InP is lattice-matched to a wider variety of materials to optimize device behavior and is thus more flexible for "bandgap engineering" than either GaAs or SiGe (SiGe is not even lattice-matched to a Si substrate, which limits the thickness of layers that can be realized). The lower surface recombination of InGaAs translates to an ability to scale transistors to obtain both higher speed and lower power relative to GaAs. Recently our laboratory demonstrated 100 GHz ft and 250 GHz fmax at 200 A of current in a sub-micrometer transistor. In addition, InGaAs is an excellent material for fabricating photodiodes for both 1310 and 1550 nm receivers. The same process that is used to make 40 Gbit/s digital circuits can yield photodiodes with 20 GHz bandwidth with only minor process modification. InP-based processes are particularly suitable for fiber-optic communication functions. Today s InP processes are capable of yielding fast ICs at moderate levels of complexity. In many data-processing applications, circuit speed can be traded for circuit complexity. Low-rate parallel processing can replace high-rate serial processing. This serial/parallel substitution is not possible in long-haul optical fiber communications, especially at the optoelectronic interface. The rapid growth in demand for data transmission requires that information travels along the fiber-optic channel at the maximum speed possible. While multiple channels in the fiber (DWDM) can increase the bandwidth, each channel still needs to be as fast as possible to obtain maximum use of the optical "pipe" while minimizing the hardware at the terminals. Until we run into a channel-spacing problem in the fiber, the data rate of each channel and the number of channels in a fiber will remain independent variables. For the foreseeable future, fiber-optic communication channels will require the fastest possible front-end electronics, combined with DWDM in extremely high throughput communication pipes. Front-end receive and transmit electronics, however, need not be particularly complex. A single high-rate channel in a fiber can be demultiplexed into many (4, 16, 64) parallel low-rate channels and the information can be processed concurrently. The technology need is, therefore, for high speed and moderate complexity. A secondary system constraint is power but only if it limits the ability to realize the overall system by impacting the compactness, reliability or module assembly. InP fits extremely well into this high speed and moderately complex niche. System constraints will often put an upper limit on chip power (e.g. 5 W/chip maximum) based on the requirements of packing density and ambient temperature. Because high speed requires high power, the complexity of the circuit is often limited by a power constraint rather than by a fabrication yield constraint. Demonstrated performance A rule of thumb for transistor performance based on the experience of previous generations of optical circuits is to use a transistor that has a cut-off frequency four times higher than the data rate. For 40 Gbit/s this means an ft of about 160 GHz. Selected circuits have been demonstrated at 40 Gbit/s with transistors of much lower performance through clever circuit design. In such designs margins often suffer and in the end the rough "4X" rule of thumb has held up. Single HBTs of InAlAs/InGaAs lattice-matched to an InP substrate can easily meet this requirement even for small, low-power devices. The unity current gain is not the only important device metric. The unity power gain cut-off, fmax, is equally important for bipolar logic circuits and is critical for distributed amplifiers. Typical results for both cut-off frequencies in our most recent generations of HBT technology are shown in . The figure shows second generation (G2) InP HBT technology, along with an enhanced version of the G2 process (G2+). High-speed transistors are a necessary, but not sufficient, condition for circuit performance. Equally important are demonstrations of benchmark circuits that simulate the requirements of transceiver components. As performance approaches the limits of the technology, certain trade-offs can be made that enhance device performance at the expense of circuit performance. We have already mentioned the ft/fmax trade-off, but more subtle trades in device design can increase both ft and fmax but reduce circuit performance. By optimizing device design for circuit performance we have demonstrated a 72.8 GHz static 1/8 divider in AlInAs/GaAs technology. Power dissipation at this upper limit of device performance was 55 mW per flip-flop. By backing off on device current density, a high performance for much less power can be achieved. A similar circuit designed for low-power operation operated at 36 GHz with a 3.1 V supply but dissipated only 6.9 mW per flip-flop half the speed at one-eighth of the power. A micrograph of the low power divider is shown in . The performance characteristics outlined here allow the realization of 4:1 MUX and 1:4 DMUX circuits dissipating only a few watts of power. The final test of the technology is the ability to realize the actual circuit functions typical in an optical transceiver. The more functions that can be integrated, the lower the system cost. We have demonstrated a number of highly integrated circuits containing many of the components required for optical communications, as well as a number of specialized circuits with low levels of integration that can be used stand-alone or integrated with more complex functions. In 1998 we demonstrated a fully integrated 7.5 Gbit/s optical receiver ASIC that monolithically integrated all the components, including the photodiode, the amplifier stage, the clock and data recovery circuit, the demultiplexer and the word-synchronization logic (Yung et al.). It consumed 3 W of power and had 2100 transistors (). This demonstration was done in our mature first generation (G1) technology with 75 GHz ft and 130 GHz fmax. Using this process in 1997, HRL also fabricated a 40 Gbit/s MUX (clocking at 20 GHz) in co-operation with Ericsson Microwave Systems and the Royal Institute of Technology in Sweden (Mokhtari et al.). More recently we fabricated smaller footprint circuits with a wider design margin, also for 40 Gbit/s applications. Lucent designed and demonstrated 40 Gbit/s MUX and DMUX circuits as well as a 74 GHz distributed amplifier in our second-generation process (Mattia et al.). The 4:1 MUX operated to 50 Gbit/s. Recently we designed and demonstrated a photonic A/D circuit in the more advanced G2 process (Broekaert et al.). The circuit consists of an optical receiver, a comparator bank and a pipelined thermometer to binary decoder. Four optical receiver pin photodiodes are integrated with the HBT process (). The bandwidth of the photodiodes is 13 GHz. The 4-bit electronic flash ADC has 3.8 effective bits at low input frequency and 2.1 effective bits at Nyquist, all at 10 GHz sampling frequency. The circuit contains about 1600 transistors, operates from a 4V supply and dissipates 6 W of power. A 3-bit electronic flash ADC has 2.8 effective bits at low input frequency and 2.4 effective bits at Nyquist at 10 GHz sampling frequency; at 18 GHz sampling frequency it has 1.7 effective bits. The 3-bit ADC has about 960 transistors, operates from a 4 V supply and dissipates 4.25 W of power. We have also demonstrated a 38 GHz MMIC VCO in AlInAs/InGaAs technology (Kurdoghlian et al.). The process and design were very robust for this type of application with extensive use of co-planar waveguide. The variation in oscillator frequency across a wafer was about 500 MHz. The designs were optimized for best phase noise and spurious characteristics. The monolithic VCO exhibited a tuning range of 850 MHz with an average output power of about +10 dBm. The phase noise performance of -82 dBc/Hz at 100 kHz offset and -108 dBc/Hz at 1 MHz offset and greater than 80% RF yield illustrates the suitability of the InP HBT technology for high-performance Ka-band and communication system applications (see ). Technology competition The technology battle lines for the next generation of optical networking chips are now being drawn. Industry heavyweights are finalizing their vision of the future of 40 Gbit/s transceivers. Some approaches combine InP and 10 Gbit/s CMOS with no SiGe, while others claim to have developed an all-SiGe solution. Many have published both SiGe and InP 40 Gbit/s developmental components. To our knowledge the only published fiber-optic long-haul demonstration system uses neither InP HBT nor SiGe circuits. Instead, small and medium-scale InP HEMTs were used for the critical components (Yoneyama et al.). A number of new players have announced their intention to compete in this market. Clearly the jury is still out on which semiconductor technology will carry the day. The battle is intense and unsettled because, for the first time, the data rates required for optical fiber electronics are approaching the maximum limits of high-speed electronics. It may be years before a clear winner emerges. Nevertheless, InP HBT technology has significant advantages over the other contenders in terms of basic transistor physics, and circuits of the speed, complexity and design margin required for 40 Gbit/s transceivers have already been demonstrated. l Further reading Baeyens et al. 2001 IEEE International Solid State Circuit Conf. Baeyens et al. 1999 Microwave and Guided Wave Lett. 9(11) 461. Broekaert et al. 2001 Journal of Solid State Circuits 36(9) 1335. Dvorak et al. 2001 Elec. Dev. Lett. 22(8) 361. Kurdoghlian et al. 2000 GaAs IC Symposium Digest 99. Lee et al. 1999 Elec. Dev. Lett. 20(8) 396. Mathew et al. 2001 Electronics Lett. 37(11) 667. Mattia et al. 1999 GaAs IC Symposium Digest 189. Mokhtari et al. 1997 Journal of Solid State Circuits 32(9) 1371. Sokolich et al. 2000 GaAs IC Symposium Digest 81. Yoneyama et al. 2000 Journal of Lightwave Technology 18(1) 34. Yung et al. 1999 Journal of Solid-State Circuits 34(2) 219.
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