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CS-MAX Brings Manufacturers Together In Silicon Valley

If you want to find out what techniques are used to manufacture all types of state-of-the-art compound semiconductor devices then CS-MAX is a good place to start, writes Jon Newey.
The second running of CS-MAX took place in San Jose, CA, on November 11-13, and pulled together 98 companies representing all of the steps in electronic and optoelectronic device manufacture into one exhibit. Many more companies contributed to the technical program that was running in parallel with the exhibit, giving manufacturers of processing tools and those that use them the chance to discuss the latest developments and how these are being brought to bear on the issues of manufacturing efficiency and enhanced device performance. As well as sessions covering generic processes such as etching, epitaxy and die separation, there were also sessions covering the manufacturing processes for specific device types including LEDs, lasers and HBTs.

Newly added to CS-MAX were sessions on silicon heterostructures, heterointegration and environmental health and safety. The health and safety session included discussions on new technologies for handling hazardous waste, and a presentation from Thales Research and Technology in France on the characterization of hazards in emerging technologies using GaN epitaxy as an example. Health and safety issues are an important consideration in overall fab management, which was another area covered at the meeting (see articles in Compound Semiconductor November 2002).

Silicon heterostructuresThe session on silicon heterostructures reflected the push of technologies developed in the compound semiconductor industry into silicon device manufacturing. Mayank Bulsara of Amberwave Systems (Salem, NH) gave an overview of strained silicon technology and its commercialization status (Compound Semiconductor September 2002 p39). Since its first demonstration in 1991, strained silicon has come to be recognized as a key to extending the silicon roadmap. It is therefore now in development at most of the major CMOS IC manufacturers and prototype circuits are emerging. The beauty of strained silicon CMOS is that it uses much of the process technology that already exists in mainstream CMOS manufacturing. However, Bulsara pointed out that the implementation of strained silicon is forcing the industry to learn about many of the techniques perfected by the compound semiconductor community for measuring and monitoring complex epilayers.

Dieter Knoll of IHP in Frankfurt, Germany, presented details of a low-cost BiCMOS process incorporating SiGe:C HBTs that has recently yielded record-breaking devices (Compound Semiconductor October 2002 p22). The process, developed jointly with Communicant Semiconductor, is relatively simple in that it dispenses with epitaxially buried sub-collectors and deep trench isolation. The BiCMOS process uses 25 lithography steps and has four metal layers to give two standard HBT variants, one optimized for speed (ft = 85 GHz, BVCEO = 2.4 V) and the other one for breakdown voltage (ft = 60 GHz, BVCEO = 3.2 V).

To enhance the RF performance of the low-cost process, the lateral dimensions of the devices can be reduced along with the emitter width, giving values for ft and fmax of 120 and 180 GHz, respectively. The BVCEO value can also be improved within the same process flow to give up to 9 V while maintaining a BVCEO x ft product of 220 GHz.

An important part of the process is the HBT-before-CMOS integration scheme. In BiCMOS processes the HBTs are inserted part way through the CMOS flow. The IHP approach of forming the HBTs before the CMOS steps eliminates the effects of the HBT thermal budget on the CMOS devices and allows easy migration of the HBT process as CMOS generations change. The scheme takes full advantage of the inherent stability of the SiGe:C HBTs and their ability to withstand the thermal impact of the CMOS processing steps.

LEDsThe two sessions on LEDs included presentations from Emcore and JPSA on the laser scribing techniques that are helping to improve yields in GaN-on-sapphire LED manufacturing. Pai Hsiang Wang of UEC in Taiwan updated delegates on the company s wafer bonded LED technology, which was announced at CS-MAX 2001 and is now being used to manufacture LEDs with 10 W power output (Compound SemiconductorDecember 2002 p25). The laser scribing and wafer bonding developments are helping to push up the all-important lumens per dollar figure by increasing LED output power and decreasing production costs.

Kelvin Shih of Lawrence Technological University, MI, described a system that he has developed for the direct measurement of the junction temperature in an LED. Previous methods of temperature measurement have been approximate, making it difficult to accurately determine the effect of junction temperature on luminous flux. Junction temperature is an important parameter as the dominant wavelength will increase by 1 nm for every 10 °C rise in junction temperature. Shih s device helps LED users and manufacturers to determine the best current at which to operate a particular model of LED in order to gain the best light power output. LED brightness increases with drive current up to a peak before tailing off as the junction temperature continues to rise. With careful LED chip and packaging design the heat can be better dissipated and the brightness at a given current can be increased.

The junction temperature measurement device uses two LEDs of the same type; the first is used as an ambient temperature reference driven at a small constant current to prevent self-heating, while the second is driven at an elevated current. The reference LED allows the measurement of the actual rather than approximate relationship between junction temperature and ambient thermal resistance in the test LED. The output of the tester can be plotted in a number of ways, including relative brightness versus current. Shih gave an example of the measurement on two Lumileds Snap 150 LEDs, the first mounted on a PCB and the second on an aluminum substrate (figure 1). For the PCB-mounted LED, the maximum brightness was obtained at 170 mA and was 4.09x that at 20 mA. The junction temperature at maximum brightness was 73 °C above ambient. For the aluminum-mounted LED, the current could be increased to 370 mA before the maximum brightness was reached. At this point the output was 9.94x that at 20 mA, yet the junction temperature was only 61 °C above ambient. Adding a good thermal conductor as a mounting reduced the thermal resistance and lowered the junction temperature for a given operating current, thus prolonging the life of the LED.

From his experiences with the tester, Shih had observed that not only do different color LEDs (AlInGaP-red and InGaN-blue, for example) behave differently, as might be expected, but those operating at the same wavelengths but manufactured by different companies also behave differently.

HeterointegrationThe integration of dissimilar materials and device types through hybrid or monolithic technologies is desirable for a number of reasons, and each method has its strengths and weaknesses. Heterogeneous integration, or heterointegration, can be thought of as sitting in between monolithic and hybrid approaches to integration. It generally involves wafer-scale processing and testing of the separate components, but also has many of the advantages of hybrid integration, including the ability to independently optimize the components before integration.

William Waters of Optogration, Newburyport, MA, discussed an epilayer transfer technique that allows the integration of an entire unprocessed epitaxial structure, such as a laser or photodiode, with a circuit or array of circuits.

Compound semiconductors on silicon (CSOS) was the subject of a talk by Fabrice Letertre of Soitec in France. Soitec s Smart Cut process for wafer bonding is used for the high-volume production of its SOI wafers. Letertre and colleagues are now extending the process to produce CSOS wafers. The Smart Cut process avoids many of the disadvantages of other techniques for producing CSOS wafers, such as complex buffer layers for epitaxial growth of GaAs-on-silicon and the expensive etch back and thus loss of the compound semiconductor wafer in thin-film transfer techniques.

The Smart Cut process involves ion implantation of the compound semiconductor wafer before it is bonded to the silicon. The bonded structure is then split along the implant peak, leaving a thin compound semiconductor layer on the silicon wafer. After polishing, the original compound semiconductor wafer can then be reused.

The process has been used to demonstrate SiC, InP, GaAs and SiGe on silicon. Letertre mainly discussed the application of Smart Cut to SiC as part of a collaborative project with CEA and LMGP labs in Grenoble, France. The group has successfully bonded 4H and 6H SiC layers to silicon using conducting and insulating bonding layers that are required for different device types (figure 2). One of the aims of the project is to provide a way of making SiC application engineered structures for GaN epitaxy, while reusing the expensive SiC wafer many times. The group has demonstrated GaN growth by MBE onto the bonded SiC layer and is currently investigating MOCVD growth.

The growth of GaAs epitaxial structures on Ge wafers is nothing new and is used in the production of very high efficiency double- and triple-junction solar cells. However, other device types manufactured using GaAs on Ge are not commercially available. Ge substrate manufacturer Umicore hopes to change attitudes and has demonstrated 6 and 8 inch Ge wafers for GaAs epitaxy. Bendix Meulemeester from Umicore discussed the production techniques for large-area Ge wafers and how the wafers could support the development of Ge-based electronics. Meulemeester reminded his audience that the first transistors were made from Ge in the 1940s. Ge channels show up to an 800% increase in carrier mobility over silicon channels, and excellent compatibility of Ge with new high-k dielectrics has been reported. However, Ge is not a common element and there is certainly not enough of it to replace silicon as a base material for microelectronics. If Ge-based devices do emerge, then they are likely to be reserved for high-end applications where cost is of less importance than performance.

CS International to return to Brussels – bigger and better than ever!

The leading global compound semiconductor conference and exhibition will once again bring together key players from across the value chain for two-days of strategic technical sessions, dynamic talks and unrivalled networking opportunities.

Join us face-to-face between 28th – 29th June 2022

  • View the agenda.
  • 3 for the price of 1. Register your place and gain complementary access to TWO FURTHER industry leading conferences: PIC International and SSI International.
  • Email  or call +44 (0)24 7671 8970 for more details.

*90% of exhibition space has gone - book your booth before it’s too late!


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