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Toshiba announces CMOS breakthroughs

Toshiba has announced two new process developments at the VLSI Symposium in Kyoto, Japan. One is a new gate dielectric, HfSiON, for 65 nm CMOS, while the other is the world's first embedded DRAM technology manufactured using SOI wafers.
Toshiba has announced a major advance in 65 nm CMOS process technology that will bring high levels of performance and low power consumption to next generation LSIs for mobile products.

Using a new high-k gate dielectric material, HfSiON, Toshiba has developed a CMOS transistor that reduces gate leakage current to a level only one-thousandth that of CMOS transistors with conventional gate dielectrics (ie SiO2).

Toshiba now plans to apply the new process to the mass production of system LSIs for mobile products in 2005.

The gate dielectric in LSI grows progressively thinner with each new generation of CMOS process technology, but this trend can lead to larger gate leakage currents. This is emerging as a critical issue, especially in lower-power products such as mobile terminals, and it has spurred a search for thicker gate dielectric materials offering the same performance as SiO2.

HfSiON is recognized as a promising alternative to SiO2, but there are few reports of any practical fabrication process that can be applied to mass production.

Toshiba has developed a fabrication process for HfSiON gate dielectric film for 65 nm low power CMOS applications and confirmed its characteristic with an experimentally fabricated LSI with 50 nm gate-length CMOS transistors. Gate leakage currents were only one-thousandth of that using SiO2 as the gate dielectric.

First embedded DRAM memory cell technology on SOI

Toshiba also announced that it has developed and verified the operability of the world s first memory cell technology for embedded DRAM system LSIs on silicon-on-insulator (SOI) wafers. Toshiba aims to apply the new technology to mass production of system LSIs for broadband network applications in 2006.

The move to ubiquitous computing-total connectivity at all times-relies on high-performance equipment. This in turn requires advanced system LSIs integrating ultra-high performance transistors and embedded high-density memory.

One promising measure to dramatically raise transistor processing speed is fabrication of system LSI on a new-generation silicon substrate, silicon-on-insulator (SOI). However, the conventional DRAM cell structure is designed for conventional bulk wafers and it is difficult to produce embedded DRAM on SOI wafer.

Toshiba has experimentally fabricated a 96 kbit cell array and verified the practical operability of the advanced cell structure with sufficient characteristics required for embedded DRAM system LSIs on SOI.

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