Europeans to develop Ge-on-insulator technology
Germanium has a higher carrier mobility than silicon for both electrons and holes, and it is expected to be compatible with high-k materials. Moreover, the dopant activation temperatures are much lower than those required by silicon, facilitating the formation of shallow junctions.
These features make germanium an excellent candidate for substrates that can be used to fabricate high-performance CMOS devices leveraging the existing silicon manufacturing infrastructure, thereby creating an urgent need for high-quality Ge-based substrates.
As part of the collaboration, Umicore will be responsible for the development and production of 200- and 300-mm Ge wafers, while Soitec will apply its expertise in fabrication methodology, using its proprietary Smart Cut process to transfer a germanium layer from these wafers to form a GeOI wafer.
IMEC will leverage its extensive knowledge of high-k materials, metal gates, device development and characterization, and process integration to develop a high-k layer deposition technique for GeOI substrates, as well as defect inspection techniques for the completed GeOI wafers. IMEC will also fabricate advanced devices to demonstrate the potential of GeOI substrates for the sub-45-nm node.
“It’s clear that innovative solutions are required to overcome the scaling challenges for sub-45nm devices. To solve the channel mobility and gate leakage current problems present in scaled silicon devices, we believe that alternative concepts such as the combination of high-k dielectrics with germanium need to be examined,” explained Gilbert Declerck, president and CEO of IMEC.
Umicore CEO Thomas Leysen noted, “This joint effort is a good example of a partnership that will help ensure the commercial viability of advanced, GeOI-based devices in a timeframe compatible with chipmakers’ accelerated time-to-market requirements.”
