IBM demonstrates the first SSDOI transistors
The improvements in carrier mobility that can be achieved using strained Si as the channel material in MOS transistors are expected to provide an answer to the problem of continuing the upward performance trend of CMOS as the Si industry approaches the fundamental limits of scaling transistor dimensions.
IBM and others have reported a 20-30 % performance enhancement in NMOS devices using strained silicon channels grown onto relaxed SiGe buffers. However, the presence of a SiGe layer causes material and process integration challenges. Several research groups including IBM, MIT and AmberWave Systems have demonstrated processes for producing SSDOI substrates, but IBM claims to be the first to fabricate transistors using SSDOI material.
The SSDOI structure was created by transferring strained Si, grown epitaxially onto a relaxed SiGe buffer, to a buried oxide layer. The SiGe layer was removed, thus creating the SSDOI material (see SSDOI process demonstration). Strain retention was confirmed in the strained Si layer after the layer transfer process and thermal cycles. Electron and hole mobility enhancements were confirmed in MOSFETs fabricated on SSDOI and fabrication of sub-60 nm FETs were also demonstrated on SSDOI.
Another way to improve CMOS performance is to increase the hole mobility in the device channels. For a given level of strain, the mobility enhancement for holes is less than that for electrons. IBM has been able to integrate devices with 2.5 times higher hole mobility into conventional CMOS technology by combining two substrates in the same wafer. This has resulted in a 40-65% performance enhancement over conventional PMOS devices.
For PFETs, hole mobility is known to be 2.5 times higher on (110) Si compared to that on standard wafer with (100) surface-orientation. IBM has created a hybrid-orientation technology (HOT) where CMOS devices are fabricated on hybrid substrate with different crystal orientations to achieve significant PFET performance enhancement. In the HOT technology, layer transfer processes, block-level trench etch, and epitaxial regrowth were performed before conventional CMOS device processing. An enhancement of 40-65% for the PFET was demonstrated on a 90 nm node CMOS technology.
IBM will present details of the two processing techniques in two papers at the International Electron Devices Meeting (IEDM) to be held in Washington, D.C. from December 7-10, 2003.
