InP/InGaAs bipolar transistors pass 500 GHz
The steady rise in the speed of bipolar transistors has largely relied on vertical scaling to reduce carrier transit time. However this comes at the cost of increasing the base-collector capacitance and reducing fmax and breakdown voltage. To compensate for this, lateral scaling of HBTs is now being addressed.
The devices were fabricated using a triple mesa design from epiwafers with a 25 nm graded base layer and 75 nm collector layer. The simultaneous achievement of a high ft and fmax (219 GHz) was attributed to the use of a micro-bridge which eliminates the base-collector capacitance inherent with designs that use large base contact posts.
A 0.35 x 12 micron device showed a current gain of 50 at Ic = 50 mA up to 68 at Ic = 25 mA. Base and collector junction ideality factors were 1.34 and 1.14 respectively. Thermal effects and gain compression limited the bandwidth of the device with Ic reaching 47.2 mA at the peak ft.
The variation of ft and fmax with emitter dimensions was also measured with the best performance coming from the 0.35 x 12 micron device. A 0.35 x 8 micron device showed ft and fmax values of 504 and 261 GHz respectively, while a 0.35 x 8 micron device gave 415 and 318 GHz. The reduction in ft with emitter size was thought to be the result of an increase in emitter metal resistance.
The work on lateral device scaling was performed as part of DARPA’s TFAST program, which is aiming improve the performance of InP HBTs through lateral scaling with the goal of taking emitter widths down to 0.15 microns and increasing the integrated transistor count of InP chips.