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SiGe BiCMOS Shines At IEDM

The 2003 IEEE International Electron Devices Meeting in Washington, DC, featured record-breaking performances in the field of BiCMOS and the first wide-channel strained-silicon devices.
As usual, the IEEE s annual International Electron Devices Meeting (IEDM), held in Washington, DC, in December, did not disappoint, with papers detailing firsts and fastests in all aspects of microelectronics. Compound semiconductors featured in three sessions and included high-speed III-V technologies and high-power wide-bandgap devices. The new material technologies for CMOS, such as high-* dielectrics and strained Si, were well represented, and developments in mixed-signal devices using SiGe HBT technology were also covered.

New oscillator record for BiCMOSSiGe BiCMOS devices are becoming established where a combination of analog and digital functions is required. Traditionally, npn bipolar devices are faster and easier to manufacture. The German development center IHP reported the development of a complementary SiGe:C BiCMOS process with pnp devices having ft and fmax of 80 and 120 GHz respectively, and npn devices with 150 and 180 GHz. In a pnp-only BiCMOS process, the ft and fmax figures were improved to 115 GHz each, the fastest pnp devices reported to date. The presence of carbon in the SiGe base has been successful in significantly reducing boron dopant out-diffusion in npn devices during subsequent thermal processes. The same mechanism also appears to pin phosphorus in the base region.

IHP reported another record from its SiGe:C BiCMOS technology - a ring oscillator with a 3.6 ps gate delay. This came about through the use of a new extrinsic base construction, which reduced the base-collector capacitance, and a low-resistance collector. The HBTs had an ft and fmax of 178 and 237 GHz respectively, with BVCEO of 1.9 V.

The growing maturity of strained Si was demonstrated with 16 papers on the subject, double the number presented in 2002. TSMC is one of the leaders in this field, with plans to make strained Si a production technology in the near future. The company s Howard Wang described a 60 nm strained Si CMOS process that yielded a ring oscillator with a 6.5 ps gate delay under 1.2 V operation. Crucially, the process was optimized to enhance its manufacturability with particular attention being paid to the effects of crystal defects.

One of the issues with strained Si has been the poor yield of wide-channel devices. Wang described the study of NMOS and PMOS device performance as a function of channel width and the role of defects in the relationship. Wide-channel devices showed a big increase in short-channel effects. Photoemission studies of the channel region showed that current leakage was highly localized in hot spots. The leakage was attributed to enhanced dopant diffusion along dislocations propagating through the channel. Defect etching confirmed the presence of dislocations at the strained Si/relaxed SiGe interface (figure 1). Statistically, narrow-channel devices would be less prone to the effects of dislocations.

The group also showed that reducing the strained Si thickness suppressed the channel-width-dependent short-channel effect, resulting in the first demonstration of wide-channel (10 µm) strained Si devices. The window for this thickness reduction is limited due to the increase in diffusion of Ge atoms to the interface between the channel and gate dielectric as the strained Si gets thinner. This diffusion introduces interface states which limit carrier mobility in the channel. However, the diffusion is thermally driven, and the group says that paying careful attention to the thermal budget allows a reasonable window for thickness reduction. The image in figure 2 shows even photoemission along the channel, indicating the absence of defects responsible for localized leakage.

Although strained Si can be produced epitaxially, strain in materials is a natural by-product of shrinking feature sizes. Process-induced strain in materials was once considered a problem, but now process-strained Si (PSS) is being taken advantage of as it can remove the need for epiwafers. TSMC s Wen-Chin Lee discussed the development of a PSS technology that uses 3D strain engineering to enhance both NMOS and PMOS devices. SiGe stressors in the source and drain regions caused strain in the x, y and z directions in the Si channel, resulting in simultaneous improvements in NMOS and PMOS devices. For a given ion, the leakage current in the off-state was 14% better for the NMOS and 22% better for PMOS devices than in unstrained control devices. Also, the PSS devices provided higher drain current at higher gate bias, unlike epitaxial substrate strained Si devices, which show diminishing performance at higher drives.

High-κ materials and Ge channelsThere were a number of papers on the subject of high-κ dielectrics, with seven devoted to HfO2, one of the favorite candidates to replace SiO2 and SiON. The main problem with using HfO2 is diffusion into the channel, which reduces mobility by 40–50%. Researchers at Intel discussed the combination of a strained Si channel with a HfO2/TiN gate stack. The gate stack was deposited directly onto the strained Si channel. Using a conventional CMOS process flow resulted in NMOS transistors with 35% higher mobility than a control device with the same gate stack and an unstrained Si channel. The HfO2 gate s equivalent oxide thickness was 1 nm and had a leakage current three orders of magnitude lower than a control device with a SiON gate insulator.

Germanium renaissance?The move away from silicon oxide, dioxide and oxynitride gates also opens the way for channel materials other than Si. The first transistors were made from Ge, and the ability to deposit high-κ dielectrics on Ge as well as Si may see its renaissance as a high-mobility channel material. Andrew Ritenour of MIT described strained Ge channel devices with HfO2 gates and TaN electrodes. While bulk Ge control devices showed a 1.4–1.8x hole mobility enhancement over bulk Si devices, the strained Ge devices showed twice the mobility of bulk Si. This mobility enhancement came despite the low level of strain in the Ge and the use of HfO2 and its associated diffusion problems.

PMOS devices are harder to fabricate using Ge because of the difficulty in n-type dopant incorporation. Chi On Chui of Stanford University reported the first Ge NMOS devices with both HfO2 and ZrO2 dielectrics. Implantation of n-type dopants into Ge results in rapid dopant diffusion due to implant damage. Phosphorus diffusion into the source-drain region was achieved through a rapid thermal anneal of P-doped SiO2, with 850 ºC for 10 s delivering the required phosphorus concentration with a sufficiently shallow junction depth.

While there is a rush to use SOI for RF devices implemented in CMOS technology, there are other approaches being investigated to place circuits in highly resistive substrates. A paper in the session on RF power and passive components dealt with the subject of substrate transfer technology (STT). This may sound like an expensive, low-yield process, but a group from Philips and Umicore believes that it has refined it to the point where it is now "just another back-end process step". Ronald Dekker from Philips explained how the process had been applied to the transfer of Si and GaAs processed wafers. In the case of Si, the process allows the transfer of RF circuits fabricated on a lossy Si substrate to an insulating glass substrate. Figure 3 shows a two-stage, 1.8 GHz power amplifier transferred to a glass carrier. The group has also applied STT to GaAs devices grown and processed on Ge substrates. The advantages here are that Ge substrates are cheaper than semi-insulating GaAs and once transfer has taken place, the Ge substrate can be reused.
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