Soitec and ASM reduce strained-SOI defects
France-based Soitec and ASM International in the Netherlands say that they have made a major breakthrough in their joint development of strained silicon-on-insulator (sSOI) technology.
Company officials say that the year-long collaborative effort has resulted in sSOI substrates that have an extremely high-quality, "wafer-level" strain, without the elevated level of crystal defects that have traditionally plagued the material.
Soitec said that the unprecedented quality of the strained layer featured defect levels reduced by a factor of between 100 and 1000 compared with the industry standard, bringing the sSOI quality close to that of standard SOI and bulk silicon.
Key to this effort, according to Soitec, was successfully introducing a "wafer-level" strain, which will extend the technology advantages well beyond the "local strain" already used in some advanced chips today.
As a result, chipmakers will have access to sSOI substrates that promise to break through today s looming barriers of power dissipation - an increasingly critical roadblock to higher-performing chips. And, since wafer-level strain is now no longer dependent on IC design, sSOI substrates will enable a wider range of high-speed, low-power IC applications, including those with high-performance logic cores.
"By successfully creating the industry s first high-quality, wafer-level sSOI technology, we have reached an important milestone in accelerating industry availability of sSOI silicon wafers and, ultimately, the future-generation chips these substrates will enable," said André Auberton-Hervé, Soitec s president and CEO.
"In addition to being the first company to offer 300 mm sSOI wafers to the industry, Soitec s roadmap calls for the first ramp of industrial-level quantities of these wafers."
The development program utilised Soitec s "Smart Cut" technology. Soitec has been sampling 200 mm sSOI for over a year, and is currently upgrading its 300 mm sSOI production line - the first of its kind worldwide - for sampling and pilot manufacturing.
The benefits afforded by wafer-level strained SOI are highly desired by the IC industry. However, a major concern about the manufacturability of this technology has been its high level of crystal defects in the wafer-level strained silicon layer; typically resulting from the epitaxial technique used to grow the SiGe templates that produce the strain on the silicon layers.
Using the Smart Cut technology has the advantage that the target high-quality epitaxial strained layer is split from the underlying high-defectivity epitaxial template and transferred to a host silicon wafer to form sSOI.
