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Epitaxy drives strained wafers to 300 mm

Strained silicon takes a big step towards industrial application with the development of 300 mm wafers suitable for future CMOS technology nodes.

Epitaxy specialist ASM International and substrate supplier Soitec have produced the first "industrially-manufactured" 300 mm strained silicon-on-insulator (sSOI) wafers.

The first wafers to incorporate the newly-engineered substrates were on show at this week s Semicon Japan show at the Makuhari Messe.

Introducing strain into silicon devices is regarded as a crucial technology that will be required to continue the march of Moore s Law into the future. While companies such as Intel have already developed commercial products that feature device-level strain to increase CMOS chip speed, strain at the wafer level is yet to be introduced as part of the manufacturing process.

Soitec s latest wafers feature a strain of 1.5 GPa, corresponding to a silicon lattice deformation of around 1%. The strained layer is 20 nm thick and is said to have a surface roughness comparable to that of the best bulk silicon wafers available.

The companies said that using ASM s Epsilon 3200 epitaxial production reactor has been a crucial factor in the development of the 300 mm wafers. The reactor is an adaptation of the company s E3000 model that is currently used for production-scale silicon epitaxy.

"Several enhancements in the E3200 [reactor] enable the growth of lattice-relaxed silicon germanium layers and strained silicon layers with unparalleled thickness and composition control," said ASM America s business unit manager for epitaxy, Armand Ferro. He added that the 300  mm wafers featured a "unique" combination of high strain and low defect density.

With the quality of the larger wafers corresponding very closely to that of the 200 mm products previously developed, Soitec says that the development demonstrates the scalability of its "Smart Cut" process to production-scale manufacturing.

"The production of 300 mm sSOI wafers takes this project beyond R&D evaluation and into the next phase of industrialization," said Carlos Mazuré, Soitec s chief technology officer.

He added that Soitec would make the wafers available for the development of ICs at the 45 nm technology node.

Following the development, France-based Soitec and ASM, The Netherlands, said that they would extend their partnership to improve manufacturing efficiency and further develop sSOI technology.

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