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Strained-silicon advance avoids SiGe epitaxy

A high-profile team comprising IBM, Advanced Micro Devices, Sony and Toshiba has developed a way to implement strain in both n-channel and p-channel silicon transistors that avoids the use of SiGe epitaxy.

Silicon chip manufacturing giant Advanced Micro Devices (AMD) says that it has found a process technology for making strained-silicon devices that does not rely on an epitaxial SiGe process.

Introducing strain into silicon chips is widely seen as a critical technology if manufacturers are to maintain the rate at which device performance has improved over the past few decades.

While the use of SiGe epitaxy is one way to speed up transistors by stretching the silicon lattice and improving carrier mobility, the AMD team, along with co-workers from IBM, Sony and Toshiba, have found a way to introduce strain without demanding significant changes to the current chip-manufacturing process.

The new process step, which is called "dual stress liner", enhances the performance of both n-channel and p-channel transistors. Silicon atoms are stretched in one transistor channel, while compressed in the other. The critical step is described in a late news paper from this year s International Electron Devices Meeting (IEDM) as follows:

"First, a highly tensile Si3N4 liner is deposited over the silicon-on-insulator (SOI) wafer. The film is then patterned and etched from PFET regions. Next, a highly compressive Si3N4 liner is deposited, and this film is then patterned and etched from NFET regions."

Developed at IBM s research center in East Fishkill, NY, the new approach results in a transistor speed increase of 24% with the same power consumption as similar devices that do not incorporate strain. It is said to be extendable to the 65 nm CMOS technology node, the next step in the chip manufacturers roadmap.

Intel has already developed and used a similar technology, albeit one that uses SiGe to generate compressive strain in the PMOS channel.

AMD says that it will gradually integrate the newly-developed technique into all of its 90 nm processor platforms, including future AMD64 chips. The US company added that the first processors to be manufactured using the dual stress liner process will be shipped in the first half of 2005.

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