News Article

TriQuint Ups PHEMT Integration

Demand for smaller, cheaper and yet more complex RF modules from cell-phone handset manufacturers is driving increased GaAs component integration and the development of disruptive RFIC technologies. Walter Wohlmuth details TriQuint's E-/D-mode PHEMT process, developed in response to that demand.

Severe pricing pressures are affecting the entire supply chain in the cellular and wireless local-area network (WLAN) industry, with GaAs chip and power-amplifier (PA) manufacturers struggling to make a profit despite booming sales of cell phones.

At the same time, products such as handsets are undergoing continuous revision, with an increasing demand for greater device functionality and complexity as additional wireless bands such as EDGE, W-CDMA/UMTS, WLAN a/b/g/n and WiMAX are accumulated.

TriQuint s latest offering, based on E-/D-mode PHEMT technology, provides one option to increase integration and reduce testing costs. The technology has advantages over competing transistor designs that use a combination of HBTs and D-mode PHEMTs and MESFETs. These include low-voltage operation, low control currents and more desirable breakdown characteristics. In production, transistors have shown consistent characteristics on epitaxy from various sources.

GaAs and silicon integration

Handsets contain a mixture of silicon and GaAs ICs. The front-end transmit-and-receive portion uses technologies such as GaAs HBTs, GaAs PHEMTs, filters and silicon LDMOS, while the transceiver and baseband elements use exclusively either silicon MOSFET or BiCMOS. The front-end transmit-and-receive modules have to accommodate PAs, antenna switches, power-control circuits, power-detect circuits, electrostatic discharge (ESD) devices, low-noise amplifiers (LNAs) and filters.

Component and configuration choices depend on the wireless bands required, the customer s design and the interface between the terminal s transceiver and baseband elements.

The general trend toward smaller, cheaper, yet more complex front-end modules has forced RFIC manufacturers into greater component integration and has promoted the acceptance of disruptive technologies. As GaAs epitaxy costs have fallen, manufacturing yields and throughput have increased. The cost of "known-good-die" testing, packaging and assembly can now exceed the basic component-fabrication expense. To combat this, device integration on a wafer can be increased, which cuts test costs and reduces module size.

The integration of HBT and FET technologies ("On-wafer device integration" table) enables a host of devices, including HBT-based PAs, FET power detect and sense circuits, FET antenna switches, FET bypass stage switches to alter PA characteristics and deliver improved efficiency at low output power and ESD protection with HBT-based implementations through pin diodes.

Since the optimum, low-cost, high-throughput method is to form a FET underneath the HBT in a single epitaxy sequence, the precise delineation of fine-line features such as gate electrodes is important. This is of most concern in high-performance antenna switch components requiring multigate structures and minimal gate-to-gate pitch to enable the trade-off of insertion loss, isolation, control current, and harmonic and cross-modulation performance. The issue also affects high-performance LNA components because gate length primarily limits low-noise performance.

E-mode PHEMTs have advantages over HBTs for PA applications: they have no thermal runaway, they exhibit softer breakdown characteristics, they do not have large voltage drops due to pn junctions and have a low turn-on voltage. They also offer easier interstage matching due to higher impedance and have high transconductance at low quiescent current, enabling sub-class B operation. However, HBT technology offers higher output power.

Integrating the E- and D-modes delivers similar circuit-building block functions to HBT and FET combinations, but benefits from a greater variety of logic architecture over a D-mode-only technology. This results in low control current logic cells and decoders.

One disadvantage of PHEMT technology is the difficulty in fabricating bias circuits that are stable in terms of process variation and temperature. ESD protection devices are also more difficult to produce in PHEMTs than in HBTs because the deep dopant layers - or regions used as current sinks to deal with the ESD pulse - are not readily available. Novel PHEMT ESD protection devices are needed instead.

Manufacturing issues

TriQuint s second-generation integrated E-/D-mode PHEMT technology uses planarizing low-k dielectrics to enable transmission line, filter, balanced/unbalanced transformer and flip-chip integration (figure 1).
Improvements delivered by this second-generation technology over its predecessor include a 20% increase in saturation drain-source current (Idss) for the D-mode devices and a 10% boost in the maximum current (Imax.). The E-mode current drive has been increased by 30%, while transconductance of the D- and E-mode devices is 5 and 12.5% higher, respectively (table 1).

Only small variations in device characteristic across each wafer and between process runs were seen, even though three different epiwafer and various substrate suppliers were used. In terms of E-mode PHEMT pinch-off voltage (Vp), the results indicate a consistent, stable, controllable process (figure 2).

Full-wafer testing of Vp from a typical run showed a standard deviation of 23 mV across a 150 mm wafer, discounting data from a 5 mm edge exclusion zone.

Device optimization required extensive cross-functional collaboration between circuit design, device modeling, device geometry and layout, unit process steps and epitaxy design. Correlation analysis between design, process, and epitaxy variants used fixed standard designs that enable on-wafer measurements, plus "known-good-die" testing and packaged testing. Significant effort improved the yield of unit process steps required to form the transistors. In certain switch components, a robust gate delineation process is required because the total gate width per wafer can be upwards of 1.3 km for 0.5 μm gate length devices with gate-gate separations of 2.0 μm.

Wafer-level and packaged-part reliability qualification tests have shown the commercial viability of a high-volume, low-cost E-/D-mode PHEMT process using multiple materials suppliers. The highly integrated components that result should improve profitability in a market faced with tough technical challenges and declining average selling prices.

CS International to return to Brussels – bigger and better than ever!

The leading global compound semiconductor conference and exhibition will once again bring together key players from across the value chain for two-days of strategic technical sessions, dynamic talks and unrivalled networking opportunities.

Join us face-to-face between 28th – 29th June 2022

  • View the agenda.
  • 3 for the price of 1. Register your place and gain complementary access to TWO FURTHER industry leading conferences: PIC International and SSI International.
  • Email  or call +44 (0)24 7671 8970 for more details.

*90% of exhibition space has gone - book your booth before it’s too late!


Search the news archive

To close this popup you can press escape or click the close icon.
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.

Please subscribe me to:


You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
Live Event