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Cree Calls The Shots At ICSCRM

At September's ICSCRM conference Cree launched 4 inch SiC material, demonstrated how to grow high-quality epitaxial layers in larger multiwafer planetary reactors, and revealed improvements in yield that are produced by reducing basal plane dislocations. Richard Stevenson reports.

Cree dominated this year s International Conference on Silicon Carbide and Related Materials (ICSCRM) in Pittsburgh, PA, using the event to reveal improvements in SiC substrate production, epitaxial growth, and the performance of various devices. The company was not to be outdone on the social front either, with all 657 delegates invited to a lavish boat party. John Palmour, Cree s director of advanced materials, even managed to rally the community with an enthusiastic, up-beat message to round off the conference - that SiC could deliver global energy savings worth $35 billion per year if these devices replaced silicon in all switch-mode power supplies and RF applications.



Cree also chose the conference to announce the commercial launch of its 100 mm n-type SiC substrates. According to Adrian Powell, these substrates have an average micropipe density below 20 cm-2 and a best value of just 0.7 cm-2, with most of the micropipes located near the wafer s edge. Powell added that Cree s 3 inch material now has an average micropipe density below 2 cm-2, a figure that is still falling, and that the best wafers have only two micropipes.



Affordable 100 mm substrates can only cut the cost of device manufacturing if they can be used in multiwafer reactors that deliver epitaxial layers of sufficient quality and uniformity. Al Burk showed that this is possible with a 8 × 100 mm warm-wall planetary reactor, using growth rates of 7-10 μm/h. This approach has produced layers on 4H-SiC substrates with nanometer-scale surface roughness as well as uniform thickness and doping.



"We chose a warm-wall reactor because it offers the optimum combination of a hot-wall and cold-wall reactor," revealed Burk, who went on to show the results for a 6.8 μm-thick doped SiC layer grown at 1600 °C. With a 3 mm exclusion zone the average variation in thickness uniformity for each 100 mm wafer, defined in terms of σ/mean, was 2%, and the difference between the thickest and thinnest wafer was 0.15 μm. For a 6 mm edge exclusion zone, mercury probe capacitance-voltage measurements revealed an average doping variation across the wafer, measured in terms of σ/mean, of less than 8%, and a wafer-to-wafer variation of ± 6%. Burk says that these results compare favorably with other published data using reactors with a lower capacity, but he added that further improvements are still required on near-edge layer uniformity and thicker layer morphology. Run-to-run uniformity also requires more investigation.

SiC for WiMAX

Cree s many presentations contained little coverage of its commercial Schottky barrier diodes (SBDs), but Palmour did outline the performance of the newer line of commercial SiC MESFETs. The company is selling 60 W MESFETs for RF applications that require a large bandwidth, such as military radios and jammers, and 10 W MESFETs for WiMAX applications. Palmour highlighted the reliability of these devices and showed that when failure is defined as a 20% change in any parameter, MESFET reliability is 250 years for an operating temperature of 175 °C, and more than 7000 years for 225 °C. "GaN can t even come close to this in terms of reliability," boasted Palmour.




The 60 W MESFETs can be employed in broadband amplifiers to deliver 12 dB from 0.85-1.6 GHz at an average power-added-efficiency of 42%, when biased at 48 V. The device linearity is 10 dB higher than that of silicon LDMOS, which ultimately leads to efficiency improvements for wireless base station transmitters.

Mrinal Das outlined Cree s development of 4H-SiC PIN diodes. The appeal of these devices is that they offer faster switching and a reduced recovery charge compared with silicon PINs, and they don t require the thick drift layers of SiC SBDs. "One problem preventing insertion into the market place is the drift in forward voltage," said Das. The increase in forward voltage is caused by the growth of stacking faults at basal plane dislocations (BPDs), which reduce the device s active area.

Das s colleague Joseph Sumakeris has developed two different approaches to reducing BPD density. According to Sumakeris, although the well known methods of using continuous epitaxial growth and depositing a thicker buffer layer do cut the number of BPDs, another "order of magnitude" improvement is still required. In one approach, called LBPD1, potassium hydroxide is used to etch the surface, then a 30 μm-thick epilayer is grown and the substrate is polished, to achieve BPD densities below 10 cm-2. Das s alternative, LBPD2, produces BPD densities of typically 20 cm-2 by hexagonal lithographic patterning of the substrate before growth. Both techniques convert the majority of BPDs into threading-edge dislocations during the initial stages of epilayer growth, which helps stop BPD dislocations spreading into the epilayers.

Das has investigated the influence of both techniques on the yield of 10 kV, 50 A 4H-SiC PIN diodes. Without these approaches, device yield, defined in terms of forward and reverse voltage performance and voltage drift, was zero. The LBPD1 and LBPD2 processes produced yields of 22% and 23%, respectively. Das is now investigating the devices long-term stability, and initial results obtained by running diodes at 10 A suggest that the potassium hydroxide etch route may be superior.

Exposing silicon s weakness

Cree s Brett Hull outlined the development of PIN diodes that operate at currents of between 2 A and 50 A and a lower blocking voltage of 6 kV, using one of the BPD density reduction techniques. Total wafer yield for 50 A diodes, which measure 8.64 mm × 8.56 mm, was 62%. This figure is only 7% lower than the yield for smaller 2 A devices, illustrating the progress made in reducing BPD. Hull also compared the switching performance of a 50 A SiC PIN with that of a commercial 4.5 kV, 60 A silicon PIN diode made by Powerex. At 150 °C the SiC PIN showed a 14% decrease in forward power loss and a 10% reduction in reverse recovery time compared with the silicon diode, and at lower temperatures the power savings were even greater.

Cree also detailed the first 1 cm × 1 cm thyristor chips that can block 5 kV and conduct 200 A. These high-current handlers can be used in flexible AC transmission systems, fault limiters and high-voltage DC transmission with advantages that include reduced cooling requirements and a potentially higher blocking voltage. A future aim, said Anant Agarwal, Cree s manager of power devices, is to develop a 20 kV thyristor with high-temperature, high-voltage packaging.

Power factor correction (PFC) circuits can also benefit from SiC. Palmour compared the performance of two PFCs that featured either silicon PINs or SiC SBDs. The devices delivered equivalent efficiency and operated at 80 kHz and 200 kHz, respectively. The SiC version was 38% smaller in terms of area and volume, and was 44% lighter.

Cree s recent advances - from material quality through to device performance - will no doubt aid the commercialization of SiC-based products. While many of these devices are still in development, in time they ought to impact the company s revenue in much the same way as its already highly successful LED chip operation.



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