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Picogiga Takes Polycrystalline Approach To SiC Substrates

The high cost of SiC substrates is hampering the commercialization of GaN-based RF devices, while silicon's low-cost platform suffers from inferior thermal conductivity. Silicon-on-polycrystalline-SiC substrates are one alternative, say Picogiga's Jean-Luc Ledys and Soitec's Fabrice Letertre.

If GaN HEMTs are to penetrate commercial RF markets such as mobile base station power amplifiers, then production costs must be comparable to those of competing technologies. While GaN HEMTs built on monocrystalline SiC substrates drive high-end performance, cost prevents them from being deployed commercially in 3G or WiMax base stations. Meanwhile, sapphire suffers from undesirable thermal properties and a significant lattice mismatch with GaN.

Cheaper GaN-on-silicon HEMTs manufactured by companies such as Nitronex and Oki Electric are starting to win customers in RF markets, but their performance is limited by the thermal properties of the silicon substrate. Consequently the market would benefit from substrates that have the physical properties of SiC, but which are available in larger sizes and at a similar cost to silicon or sapphire wafers.

Choosing a substrate

For RF applications, the ideal substrate should be electrically insulating, contribute little RF loss, and provide a seed layer that is sufficient to grow a high-quality active layer. It should also deliver high thermal conductivity, so that heat generated by the transistor is dissipated efficiently. This thermal management ensures long-term reliability and enables the device to maintain its maximum output power.

These criteria are being addressed by Soitec Group and its specialist GaN division, Picogiga International. Soitec has developed four substrates to deliver cost-effective seed layers that can be used to grow low-defect-density GaN HEMTs. These are GaN-on-silicon, SiC-on-insulator (SiCOI), GaN-on-insulator (GaNOI), and silicon-on-polycrystalline-SiC (SopSiC).

To produce GaN-on-silicon wafers, Soitec uses high-resistivity silicon (HRSi) substrates. This material is highly affordable, available in diameters of up to 6 inches, and offers the cheapest route to manufacturing GaN HEMTs. Soitec s patented MBE epitaxial growth method enables GaN to be deposited directly onto silicon despite the lattice mismatch, while maintaining an acceptable level of defect density. However, this substrate s thermal conductivity limits device performance and so it is not ideal for high-power applications.

The other three types of substrate are produced by combining MBE-based epitaxial growth with a proprietary Smart Cut layer-transfer and wafer-bonding technology (figure 1). The process has been used to produce robust 4-12 inch diameter silicon-on-insulator wafers in high volumes for more than 10 years. The multilayer structure of the wafers enables the seed material on the substrate s front side and the carrier material on its back side to be optimized independently.

At the moment SiCOI and GaNOI wafers are limited in size because large-diameter GaN and SiC substrates are not available, but in time bigger versions will reach the market-place. These wafers are formed by taking thin slices of either SiC or GaN from bulk substrates, and then bonding these layers to insulating material.

The SiCOI wafers, whose base substrates are made from oxidized silicon, offer affordable templates that deliver a GaN crystalline quality that is equivalent to GaN films grown on SiC, as well as a substrate holder that has better handling characteristics than bulk SiC.

The GaNOI substrates enable the homoepitaxial growth of very high-quality GaN films. However, this technique is restricted by the shortage of high-quality GaN bulk material: only nine vendors exist worldwide and prices are high. There are also difficulties associated with preparing the GaN surface before bonding. The Smart Cut process requires the GaN s back side to be polished to a mirror-like flatness so that the wafer can bond to the substrate holder, but it is not yet possible to achieve this with a process that is suitable for volume manufacturing.

SopSiC: the Smart Cut approach

One promising alternative to using bulk silicon substrates in the manufacture of GaN HEMTs are SopSiC substrates. Soitec s Smart Cut technology can be employed to produce large volumes of SopSiC wafers up to 6 inches in diameter, and could therefore enable GaN HEMTs to be produced cost effectively. The starting materials for SopSiC substrates are a polycrystalline cubic SiC substrate and an HRSi (111) wafer produced by the Czochralski technique, both of which are available in sizes ranging from 2 to 12 inches.

The morphological properties of the HRSi (111) seed layer have been investigated extensively. High-resolution X-ray diffraction and Raman spectroscopy measurements have revealed that the silicon layer has a crystalline quality and stress levels similar to those of bulk silicon. The layer also exhibits excellent thickness uniformity (figure 2) and an "angstrom range" surface roughness that is ideal for GaN epitaxial growth.

Polycrystalline SiC is highly resistive (>105 Ωcm), and has thermal and mechanical characteristics that are comparable to those of single-crystal SiC. It has a thermal conductivity of 3 W/Kcm that even surpasses the conductivity of GaN (table 1). Polycrystalline SiC can be produced by chemical vapor deposition, and the material has been widely used for microelectronic applications where it serves as 2-12 inch dummy wafers. It costs only two to three times as much as silicon, its resistivity can be easily tuned from 1.5 × 10-2 Ωcm to 1  × 109 Ωcm, and RF losses can be adjusted
to be as low as those of GaAs substrates.

Thermal simulations of the junction temperature of GaN transistors fabricated on various substrates suggest that SopSiC will deliver thermal capabilities close to those of polycrystalline SiC, and will dissipate heat more efficiently than bulk silicon (figure 3).

Structures fabricated on SopSiC and bulk silicon exhibit fairly similar results, indicating that the seed layer dominates the performance, whether it is in bulk form or has been transferred by Smart Cut technology (table 2). The same observations occur for structures grown on SiCOI and SiC substrates.

Although devices fabricated on SopSiC and SiCOI are still to be fully characterized, initial results suggest that the back side appears to have little influence on the RF and DC characteristics, although it strongly influences the device s thermal properties. Recent publications (see further reading) also suggest that GaN devices grown on SiC can deliver similar RF and DC results to devices grown using silicon seed layers. Although X-ray diffraction and defect-density measurements suggest that the GaN/AlGaN crystalline quality is higher on SiC substrates, the improvement seems to be insufficient to deliver gains to RF and DC parameters.

Consequently, any advantages introduced by the back side material in a Smart Cut substrate, such as the thermal conductivity advantages offered by porous SiC over silicon, will only improve the behaviour of RF power devices in terms of maximum operating power, operating temperature and reliability. These gains will help to close the gap with devices built on SiC in a cost-effective way.

However, special care is required to prevent multilayer substrates from adversely affecting the device s RF behaviour. HRSi and polycrystalline SiC can be engineered to reduce their RF losses to levels below those of semi-insulating GaAs substrates for frequencies
of up to 40 GHz (figure 4). This refinement enables GaN HEMTs produced with Smart Cut technology to cover a range of applications including radar (X and S band), satellite communications, 3G mobile communications infrastructures, and WiMAX base stations.

Further reading

H Lahreche et al. Materials Science Forum 457-460 1621.

D C Dumka et al. 2004 Electron. Lett. 40 1023.

F Letertre et al. 2005, 207th ECS Meeting, Quebec.

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