Expanding Soitec Debuts Strained-SOI Substrates
Advanced materials specialist Soitec has launched the industry's first line of commercial strained silicon-on-insulator (sSOI) substrates.
Targeting device manufacturers focused on high-speed applications such as network processing, computing, gaming and high-end wireless connectivity, the French firm says that the wafers are available now for sub-65 nm CMOS processing.
sSOI specialist Suresh Venkatesan from Freescale says that as well as providing an increase in transistor speeds, the technology will help to reduce power consumption in both active and standby operating modes.
"While this technology is currently under evaluation for the 45 nm node, initially for networking and gaming applications, it could eventually help Freescale's customers create dramatically smaller and more powerful and intelligent portable devices," said Venkatesan.
Having recently transferred its 300 mm sSOI wafers from development into initial production runs, Soitec is also about to break ground on a new facility in Singapore. This fab will be ready to produce 300 mm regular SOI wafers from mid-2008 onwards.
Soitec is also involved in a huge research project focused on developing new applications for the "Smart Cut" technology that it uses to manufacture the sSOI wafers.
The NanoSmart project, which is expected to have a total budget of €170 million ($216 million) and will be carried out in collaboration with the CEA Léti research center, is expected to require an additional 100 researchers over a five-year period.
Soitec's III-V material subsidiary Picogiga is also working on GaN-on-insulator (GaNOI) substrate material that is fabricated using the Smart Cut process (see related story).