Skyworks Favors Hybrid BiFET Design
It s a competitive market for the manufacturers of GaAs-based chips for cell phones. Prices are eroding, and handset designers are demanding smaller components. So chipmakers must innovate to remain profitable, by developing products with a smaller footprint and cheaper material costs, or more advanced modules with greater functionality that can command a higher price tag.
Skyworks has been pursuing both of these strategies. According to Steve Machuga, vice-president of RF front-end development for Skyworks Mobile Platforms business, the Woburn-based outfit initially invested in design approaches that minimized the GaAs footprint in the phone, and this led to power amplifier (PA) costs that were close to those of their silicon counterparts. However, the firm has since shifted direction with the development of more sophisticated components, culminating in last year s launch of a range of BiFET chips featuring HBTs and FETs on the same die.
"The BiFET technology is an example of where we ve been able to integrate an FET, for use in bias control circuits, at almost no extra incremental cost to the core HBT technology," says Machuga. The bias control circuit manages the PA s performance more efficiently, which leads to longer handset talk times.
BiFETs can be built using either a monolithic or a hybrid design, and Skyworks has evaluated both types of device (see "Different approaches to BiFET design"). The company rejected the monolithic design and selected a hybrid design for manufacturing all of its BiFETs, which positions the FET on top of the HBT.
"Our motivation for choosing this approach is very simple," explains Ravi Ramanathan, Skyworks manager of compound semiconductors advanced process technology. "We want to use a simple process that does not increase the epitaxial and processing costs, and a low-performance DC-type switch for bias control."
Skyworks believes that the benefits of the hybrid design include quick lot (QL) characterization of the HBT and FET, shared processing steps, a minimal impact on total processing time compared with stand-alone HBT manufacture, and the need for only two additional masking layers to define the FET. This device has its limitations, though, such as poor RF isolation and a compatibility with only n-type FETs.
The monolithic design, which is used by Skyworks rival Anadigics, allows independent tuning of the FET and HBT, so that individual device characteristics can be tuned to the needs of the application. However, Skyworks claims that this design cannot be used for profitable manufacturing in today s market. Drawbacks include complex QL characterization procedures that can require further process steps, complicated electrolytic capacitance-voltage (C-V) profiling, and a longer "stabilization bake" step for the FET that increases the time to manufacture the final product.
With the monolithic design the BiFET s emitter and gate are typically separated by a few microns but have micron-sized heights differences, says Ramanathan, making it awkward to carry out the sub-micron-sized photolithographic process used for device manufacture. "You need a very high planarizing resist process, but the resist thickness will increase and reduce the line-width resolution, or you need to move the FET substantially further away from the HBT, to eliminate severe topology effects on the gate process," explains Ramanathan.
Anadigics, which has been manufacturing BiFET-based chips in volume since 2003, rebuts Skyworks assessment of the monolithic design, claiming that all of the concerns "are either incorrect or do not apply". According to the Warren, NJ, company, its InGaP-based technology provides product performance and integration improvements with no impact on either yield or cycle times. The devices are also more versatile than Skyworks because PHEMT and MESFET structures can be constructed below the collector, says Anadigics, and the BiFETs offer an equivalent performance to stand-alone InGaP and PHEMT structures.
Anadigics also claims that its BiFET manufacture requires just two additional mask levels compared with a traditional InGaP HBT process, which is the same added complexity as Skyworks BiFET process. Also, its chips do not need complex characterization procedures or a long stabilization bake. "The products are competitively priced in the market," says an Anadigics spokesperson, and its rising revenue and gross margin also suggest that a greater proportion of InGaP-based products in the company s sales mix is actually boosting its financial performance.
Skyworks, like Anadigics, does not produce its material in-house, and outsources growth to Kopin. The epiwafer supplier carries out a series of QL tests on large-area devices, which are typically 75 × 75 µm, to determine if the material s quality is suitable for chip production. These measurements reveal the DC gain, offset voltage, base-emitter and base-collector turn-on voltages, and junction breakdown voltages. However, because FETs are sensitive to process conditions that can mask growth variations, Kopin cannot predict the pinch-off voltage, saturation current and transconductance of BiFETs made from these epiwafers.
To overcome these issues associated with measuring the FET performance, Kopin and Skyworks have established a QL procedure based on C-V measurements that identifies run-to-run and machine-to-machine variations. Profiles of the emitter-base junctions reveal the FET s channel thickness and doping concentration, which are related to the characteristics of the fully processed FET.
The epiwafer batches that pass all the QL tests at Kopin are shipped to Skyworks and processed into BiFETs. Ramanathan says that the Ti/Pt/Au/Ti Schottky gate contact, which is formed by metal evaporation onto the channel layer, is the key component and is extremely sensitive to the gate processing steps.
Skyworks has evaluated gates produced by both photolithography and etching. The former approach produces a gate that is free from cracks and which allows SiN passivation on the gate metal, but it can also lead to Schottky contacts with undesired characteristics due to "gate sinking" and gold and platinum diffusion into the channel. As a result, Skyworks employs an etching process for BiFET manufacture that circumvents these problems, and also allows for gates with thicker gold layers that reduce contact resistance.
Skyworks has assessed its BiFET manufacturing yield by measuring 40–50 parameters related to the FET, HBT or the passive components. With a yield that is routinely above 95%, very little material is wasted in the production process.